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11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14
15#define CONFIG_SYS_BOOK3E_HV
16#define CONFIG_MP
17#define CONFIG_ENABLE_36BIT_PHYS
18
19#ifdef CONFIG_PHYS_64BIT
20#define CONFIG_ADDR_MAP 1
21#define CONFIG_SYS_NUM_ADDR_MAP 64
22#endif
23
24#define CONFIG_SYS_FSL_CPC
25#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26#define CONFIG_FSL_IFC
27
28#define CONFIG_ENV_OVERWRITE
29
30#define CONFIG_FSL_CAAM
31
32
33#ifdef CONFIG_ARCH_T1024
34#define CONFIG_DEEP_SLEEP
35#endif
36#if defined(CONFIG_DEEP_SLEEP)
37#define CONFIG_BOARD_EARLY_INIT_F
38#endif
39
40#ifdef CONFIG_RAMBOOT_PBL
41#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
42#define CONFIG_SPL_FLUSH_IMAGE
43#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
44#define CONFIG_SYS_TEXT_BASE 0x30001000
45#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
46#define CONFIG_SPL_PAD_TO 0x40000
47#define CONFIG_SPL_MAX_SIZE 0x28000
48#define RESET_VECTOR_OFFSET 0x27FFC
49#define BOOT_PAGE_OFFSET 0x27000
50#ifdef CONFIG_SPL_BUILD
51#define CONFIG_SPL_SKIP_RELOCATE
52#define CONFIG_SPL_COMMON_INIT_DDR
53#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
54#define CONFIG_SYS_NO_FLASH
55#endif
56
57#ifdef CONFIG_NAND
58#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
59#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
60#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
61#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
62#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63#if defined(CONFIG_TARGET_T1024RDB)
64#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
65#elif defined(CONFIG_TARGET_T1023RDB)
66#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
67#endif
68#define CONFIG_SPL_NAND_BOOT
69#endif
70
71#ifdef CONFIG_SPIFLASH
72#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
73#define CONFIG_SPL_SPI_FLASH_MINIMAL
74#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
75#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
76#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
77#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
78#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
79#ifndef CONFIG_SPL_BUILD
80#define CONFIG_SYS_MPC85XX_NO_RESETVEC
81#endif
82#if defined(CONFIG_TARGET_T1024RDB)
83#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
84#elif defined(CONFIG_TARGET_T1023RDB)
85#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
86#endif
87#define CONFIG_SPL_SPI_BOOT
88#endif
89
90#ifdef CONFIG_SDCARD
91#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
92#define CONFIG_SPL_MMC_MINIMAL
93#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
94#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
95#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
96#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
97#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
98#ifndef CONFIG_SPL_BUILD
99#define CONFIG_SYS_MPC85XX_NO_RESETVEC
100#endif
101#if defined(CONFIG_TARGET_T1024RDB)
102#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
103#elif defined(CONFIG_TARGET_T1023RDB)
104#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
105#endif
106#define CONFIG_SPL_MMC_BOOT
107#endif
108
109#endif
110
111#ifndef CONFIG_SYS_TEXT_BASE
112#define CONFIG_SYS_TEXT_BASE 0xeff40000
113#endif
114
115#ifndef CONFIG_RESET_VECTOR_ADDRESS
116#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117#endif
118
119#ifndef CONFIG_SYS_NO_FLASH
120#define CONFIG_FLASH_CFI_DRIVER
121#define CONFIG_SYS_FLASH_CFI
122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123#endif
124
125
126#define CONFIG_SRIO_PCIE_BOOT_MASTER
127
128
129
130
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
132#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
133#ifdef CONFIG_PHYS_64BIT
134#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
135#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
136#else
137#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
138#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
139#endif
140
141
142
143
144#ifdef CONFIG_PHYS_64BIT
145#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
146#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
147#else
148#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
149#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
150#endif
151#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
152
153#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
154#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
155
156
157#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
158#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
159#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
161
162#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
163#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
164 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
165#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
166#define CONFIG_SYS_NO_FLASH
167#endif
168
169#if defined(CONFIG_SPIFLASH)
170#define CONFIG_SYS_EXTRA_ENV_RELOC
171#define CONFIG_ENV_IS_IN_SPI_FLASH
172#define CONFIG_ENV_SPI_BUS 0
173#define CONFIG_ENV_SPI_CS 0
174#define CONFIG_ENV_SPI_MAX_HZ 10000000
175#define CONFIG_ENV_SPI_MODE 0
176#define CONFIG_ENV_SIZE 0x2000
177#define CONFIG_ENV_OFFSET 0x100000
178#if defined(CONFIG_TARGET_T1024RDB)
179#define CONFIG_ENV_SECT_SIZE 0x10000
180#elif defined(CONFIG_TARGET_T1023RDB)
181#define CONFIG_ENV_SECT_SIZE 0x40000
182#endif
183#elif defined(CONFIG_SDCARD)
184#define CONFIG_SYS_EXTRA_ENV_RELOC
185#define CONFIG_ENV_IS_IN_MMC
186#define CONFIG_SYS_MMC_ENV_DEV 0
187#define CONFIG_ENV_SIZE 0x2000
188#define CONFIG_ENV_OFFSET (512 * 0x800)
189#elif defined(CONFIG_NAND)
190#define CONFIG_SYS_EXTRA_ENV_RELOC
191#define CONFIG_ENV_IS_IN_NAND
192#define CONFIG_ENV_SIZE 0x2000
193#if defined(CONFIG_TARGET_T1024RDB)
194#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
195#elif defined(CONFIG_TARGET_T1023RDB)
196#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
197#endif
198#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
199#define CONFIG_ENV_IS_IN_REMOTE
200#define CONFIG_ENV_ADDR 0xffe20000
201#define CONFIG_ENV_SIZE 0x2000
202#elif defined(CONFIG_ENV_IS_NOWHERE)
203#define CONFIG_ENV_SIZE 0x2000
204#else
205#define CONFIG_ENV_IS_IN_FLASH
206#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
207#define CONFIG_ENV_SIZE 0x2000
208#define CONFIG_ENV_SECT_SIZE 0x20000
209#endif
210
211#ifndef __ASSEMBLY__
212unsigned long get_board_sys_clk(void);
213unsigned long get_board_ddr_clk(void);
214#endif
215
216#define CONFIG_SYS_CLK_FREQ 100000000
217#define CONFIG_DDR_CLK_FREQ 100000000
218
219
220
221
222#define CONFIG_SYS_CACHE_STASHING
223#define CONFIG_BACKSIDE_L2_CACHE
224#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
225#define CONFIG_BTB
226#define CONFIG_DDR_ECC
227#ifdef CONFIG_DDR_ECC
228#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
229#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
230#endif
231
232#define CONFIG_SYS_MEMTEST_START 0x00200000
233#define CONFIG_SYS_MEMTEST_END 0x00400000
234#define CONFIG_SYS_ALT_MEMTEST
235#define CONFIG_PANIC_HANG
236
237
238
239
240#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
241#define CONFIG_SYS_L3_SIZE (256 << 10)
242#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
243#ifdef CONFIG_RAMBOOT_PBL
244#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
245#endif
246#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
247#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
248#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
249#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
250
251#ifdef CONFIG_PHYS_64BIT
252#define CONFIG_SYS_DCSRBAR 0xf0000000
253#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
254#endif
255
256
257#define CONFIG_ID_EEPROM
258#define CONFIG_SYS_I2C_EEPROM_NXID
259#define CONFIG_SYS_EEPROM_BUS_NUM 0
260#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
261#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
262#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
263#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
264
265
266
267
268#define CONFIG_VERY_BIG_RAM
269#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
270#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
271#define CONFIG_DIMM_SLOTS_PER_CTLR 1
272#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
273#define CONFIG_FSL_DDR_INTERACTIVE
274#if defined(CONFIG_TARGET_T1024RDB)
275#define CONFIG_DDR_SPD
276#define CONFIG_SYS_SPD_BUS_NUM 0
277#define SPD_EEPROM_ADDRESS 0x51
278#define CONFIG_SYS_SDRAM_SIZE 4096
279#elif defined(CONFIG_TARGET_T1023RDB)
280#define CONFIG_SYS_DDR_RAW_TIMING
281#define CONFIG_SYS_SDRAM_SIZE 2048
282#endif
283
284
285
286
287#define CONFIG_SYS_FLASH_BASE 0xe8000000
288#ifdef CONFIG_PHYS_64BIT
289#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
290#else
291#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
292#endif
293
294#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
295#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
296 CSPR_PORT_SIZE_16 | \
297 CSPR_MSEL_NOR | \
298 CSPR_V)
299#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
300
301
302#if defined(CONFIG_TARGET_T1024RDB)
303#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
304#elif defined(CONFIG_TARGET_T1023RDB)
305#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
306 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
307#endif
308#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
309 FTIM0_NOR_TEADC(0x5) | \
310 FTIM0_NOR_TEAHC(0x5))
311#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
312 FTIM1_NOR_TRAD_NOR(0x1A) |\
313 FTIM1_NOR_TSEQRAD_NOR(0x13))
314#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
315 FTIM2_NOR_TCH(0x4) | \
316 FTIM2_NOR_TWPH(0x0E) | \
317 FTIM2_NOR_TWP(0x1c))
318#define CONFIG_SYS_NOR_FTIM3 0x0
319
320#define CONFIG_SYS_FLASH_QUIET_TEST
321#define CONFIG_FLASH_SHOW_PROGRESS 45
322
323#define CONFIG_SYS_MAX_FLASH_BANKS 1
324#define CONFIG_SYS_MAX_FLASH_SECT 1024
325#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
326#define CONFIG_SYS_FLASH_WRITE_TOUT 500
327
328#define CONFIG_SYS_FLASH_EMPTY_INFO
329#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
330
331#ifdef CONFIG_TARGET_T1024RDB
332
333#define CONFIG_SYS_CPLD_BASE 0xffdf0000
334#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
335#define CONFIG_SYS_CSPR2_EXT (0xf)
336#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
337 | CSPR_PORT_SIZE_8 \
338 | CSPR_MSEL_GPCM \
339 | CSPR_V)
340#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
341#define CONFIG_SYS_CSOR2 0x0
342
343
344#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
345 FTIM0_GPCM_TEADC(0x0e) | \
346 FTIM0_GPCM_TEAHC(0x0e))
347#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
348 FTIM1_GPCM_TRAD(0x1f))
349#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
350 FTIM2_GPCM_TCH(0x8) | \
351 FTIM2_GPCM_TWP(0x1f))
352#define CONFIG_SYS_CS2_FTIM3 0x0
353#endif
354
355
356#define CONFIG_NAND_FSL_IFC
357#define CONFIG_SYS_NAND_BASE 0xff800000
358#ifdef CONFIG_PHYS_64BIT
359#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
360#else
361#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
362#endif
363#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
364#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
365 | CSPR_PORT_SIZE_8 \
366 | CSPR_MSEL_NAND \
367 | CSPR_V)
368#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
369
370#if defined(CONFIG_TARGET_T1024RDB)
371#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
372 | CSOR_NAND_ECC_DEC_EN \
373 | CSOR_NAND_ECC_MODE_4 \
374 | CSOR_NAND_RAL_3 \
375 | CSOR_NAND_PGS_4K \
376 | CSOR_NAND_SPRZ_224 \
377 | CSOR_NAND_PB(64))
378#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
379#elif defined(CONFIG_TARGET_T1023RDB)
380#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
381 | CSOR_NAND_ECC_DEC_EN \
382 | CSOR_NAND_ECC_MODE_4 \
383 | CSOR_NAND_RAL_3 \
384 | CSOR_NAND_PGS_2K \
385 | CSOR_NAND_SPRZ_128 \
386 | CSOR_NAND_PB(64))
387#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
388#endif
389
390#define CONFIG_SYS_NAND_ONFI_DETECTION
391
392#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
393 FTIM0_NAND_TWP(0x18) | \
394 FTIM0_NAND_TWCHT(0x07) | \
395 FTIM0_NAND_TWH(0x0a))
396#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
397 FTIM1_NAND_TWBE(0x39) | \
398 FTIM1_NAND_TRR(0x0e) | \
399 FTIM1_NAND_TRP(0x18))
400#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
401 FTIM2_NAND_TREH(0x0a) | \
402 FTIM2_NAND_TWHRE(0x1e))
403#define CONFIG_SYS_NAND_FTIM3 0x0
404
405#define CONFIG_SYS_NAND_DDR_LAW 11
406#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
407#define CONFIG_SYS_MAX_NAND_DEVICE 1
408#define CONFIG_CMD_NAND
409
410#if defined(CONFIG_NAND)
411#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
412#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
413#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
414#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
415#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
416#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
417#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
418#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
419#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
420#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
421#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
422#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
423#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
424#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
425#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
426#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
427#else
428#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
429#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
430#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
431#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
432#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
433#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
434#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
435#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
436#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
437#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
438#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
439#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
440#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
441#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
442#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
443#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
444#endif
445
446#ifdef CONFIG_SPL_BUILD
447#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
448#else
449#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
450#endif
451
452#if defined(CONFIG_RAMBOOT_PBL)
453#define CONFIG_SYS_RAMBOOT
454#endif
455
456#define CONFIG_BOARD_EARLY_INIT_R
457#define CONFIG_MISC_INIT_R
458
459#define CONFIG_HWCONFIG
460
461
462#define CONFIG_L1_INIT_RAM
463#define CONFIG_SYS_INIT_RAM_LOCK
464#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
465#ifdef CONFIG_PHYS_64BIT
466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
467#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
468
469#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
470 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
471 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
472#else
473#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
474#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
475#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
476#endif
477#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
478
479#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
480 GENERATED_GBL_DATA_SIZE)
481#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
482
483#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
484#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
485
486
487#define CONFIG_CONS_INDEX 1
488#define CONFIG_SYS_NS16550_SERIAL
489#define CONFIG_SYS_NS16550_REG_SIZE 1
490#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
491
492#define CONFIG_SYS_BAUDRATE_TABLE \
493 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
494
495#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
496#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
497#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
498#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
499
500
501#undef CONFIG_FSL_DIU_FB
502#ifdef CONFIG_FSL_DIU_FB
503#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
504#define CONFIG_CMD_BMP
505#define CONFIG_VIDEO_LOGO
506#define CONFIG_VIDEO_BMP_LOGO
507#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
508
509
510
511
512#undef CONFIG_SYS_FLASH_EMPTY_INFO
513#endif
514
515
516#define CONFIG_SYS_I2C
517#define CONFIG_SYS_I2C_FSL
518#define CONFIG_SYS_FSL_I2C_SPEED 50000
519#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
520#define CONFIG_SYS_FSL_I2C2_SPEED 50000
521#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
522#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
523#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
524
525#define I2C_PCA6408_BUS_NUM 1
526#define I2C_PCA6408_ADDR 0x20
527
528
529#define I2C_MUX_CH_DEFAULT 0x8
530
531
532
533
534#define RTC
535#define CONFIG_RTC_DS1337 1
536#define CONFIG_SYS_I2C_RTC_ADDR 0x68
537
538
539
540
541#define CONFIG_SPI_FLASH_BAR
542#define CONFIG_SF_DEFAULT_SPEED 10000000
543#define CONFIG_SF_DEFAULT_MODE 0
544
545
546
547
548
549#define CONFIG_PCIE1
550#define CONFIG_PCIE2
551#define CONFIG_PCIE3
552#ifdef CONFIG_ARCH_T1040
553#define CONFIG_PCIE4
554#endif
555#define CONFIG_FSL_PCI_INIT
556#define CONFIG_SYS_PCI_64BIT
557#define CONFIG_PCI_INDIRECT_BRIDGE
558
559#ifdef CONFIG_PCI
560
561#ifdef CONFIG_PCIE1
562#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
563#ifdef CONFIG_PHYS_64BIT
564#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
565#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
566#else
567#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
568#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
569#endif
570#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
571#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
572#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
573#ifdef CONFIG_PHYS_64BIT
574#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
575#else
576#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
577#endif
578#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
579#endif
580
581
582#ifdef CONFIG_PCIE2
583#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
584#ifdef CONFIG_PHYS_64BIT
585#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
586#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
587#else
588#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
589#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
590#endif
591#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
592#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
593#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
594#ifdef CONFIG_PHYS_64BIT
595#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
596#else
597#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
598#endif
599#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
600#endif
601
602
603#ifdef CONFIG_PCIE3
604#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
605#ifdef CONFIG_PHYS_64BIT
606#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
607#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
608#else
609#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
610#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
611#endif
612#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
613#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
614#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
615#ifdef CONFIG_PHYS_64BIT
616#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
617#else
618#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
619#endif
620#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
621#endif
622
623
624#ifdef CONFIG_PCIE4
625#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
626#ifdef CONFIG_PHYS_64BIT
627#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
628#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
629#else
630#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
631#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
632#endif
633#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
634#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
635#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
636#ifdef CONFIG_PHYS_64BIT
637#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
638#else
639#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
640#endif
641#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
642#endif
643
644#define CONFIG_PCI_SCAN_SHOW
645#define CONFIG_DOS_PARTITION
646#endif
647
648
649
650
651#define CONFIG_HAS_FSL_DR_USB
652
653#ifdef CONFIG_HAS_FSL_DR_USB
654#define CONFIG_USB_EHCI
655#define CONFIG_USB_EHCI_FSL
656#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
657#endif
658
659
660
661
662#ifdef CONFIG_MMC
663#define CONFIG_FSL_ESDHC
664#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
665#define CONFIG_GENERIC_MMC
666#define CONFIG_DOS_PARTITION
667#endif
668
669
670#ifndef CONFIG_NOBQFMAN
671#define CONFIG_SYS_DPAA_QBMAN
672#define CONFIG_SYS_BMAN_NUM_PORTALS 10
673#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
674#ifdef CONFIG_PHYS_64BIT
675#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
676#else
677#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
678#endif
679#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
680#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
681#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
682#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
683#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
684#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
685 CONFIG_SYS_BMAN_CENA_SIZE)
686#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
687#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
688#define CONFIG_SYS_QMAN_NUM_PORTALS 10
689#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
690#ifdef CONFIG_PHYS_64BIT
691#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
692#else
693#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
694#endif
695#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
696#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
697#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
698#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
699#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
700#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
701 CONFIG_SYS_QMAN_CENA_SIZE)
702#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
703#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
704
705#define CONFIG_SYS_DPAA_FMAN
706
707#ifdef CONFIG_TARGET_T1024RDB
708#define CONFIG_QE
709#define CONFIG_U_QE
710#endif
711
712#if defined(CONFIG_SPIFLASH)
713
714
715
716
717#define CONFIG_SYS_QE_FW_IN_SPIFLASH
718#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
719#define CONFIG_SYS_QE_FW_ADDR 0x130000
720#elif defined(CONFIG_SDCARD)
721
722
723
724
725
726#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
727#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
728#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
729#elif defined(CONFIG_NAND)
730#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
731#if defined(CONFIG_TARGET_T1024RDB)
732#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
733#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
734#elif defined(CONFIG_TARGET_T1023RDB)
735#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
736#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
737#endif
738#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
739
740
741
742
743
744
745
746#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
747#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
748#else
749#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
750#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
751#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
752#endif
753#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
754#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
755#endif
756
757#ifdef CONFIG_SYS_DPAA_FMAN
758#define CONFIG_FMAN_ENET
759#define CONFIG_PHYLIB_10G
760#define CONFIG_PHY_REALTEK
761#define CONFIG_PHY_AQUANTIA
762#if defined(CONFIG_TARGET_T1024RDB)
763#define RGMII_PHY1_ADDR 0x2
764#define RGMII_PHY2_ADDR 0x6
765#define SGMII_AQR_PHY_ADDR 0x2
766#define FM1_10GEC1_PHY_ADDR 0x1
767#elif defined(CONFIG_TARGET_T1023RDB)
768#define RGMII_PHY1_ADDR 0x1
769#define SGMII_RTK_PHY_ADDR 0x3
770#define SGMII_AQR_PHY_ADDR 0x2
771#endif
772#endif
773
774#ifdef CONFIG_FMAN_ENET
775#define CONFIG_MII
776#define CONFIG_ETHPRIME "FM1@DTSEC4"
777#define CONFIG_PHY_GIGE
778#endif
779
780
781
782
783#ifndef CONFIG_SYS_NO_FLASH
784#define CONFIG_MTD_DEVICE
785#define CONFIG_MTD_PARTITIONS
786#define CONFIG_CMD_MTDPARTS
787#define CONFIG_FLASH_CFI_MTD
788#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
789 "spi0=spife110000.1"
790#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
791 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
792 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
793 "1m(uboot),5m(kernel),128k(dtb),-(user)"
794#endif
795
796
797
798
799#define CONFIG_LOADS_ECHO
800#define CONFIG_SYS_LOADS_BAUD_CHANGE
801
802
803
804
805#define CONFIG_CMD_DATE
806#define CONFIG_CMD_EEPROM
807#define CONFIG_CMD_ERRATA
808#define CONFIG_CMD_IRQ
809#define CONFIG_CMD_REGINFO
810
811#ifdef CONFIG_PCI
812#define CONFIG_CMD_PCI
813#endif
814
815
816
817
818#define CONFIG_SYS_LONGHELP
819#define CONFIG_CMDLINE_EDITING
820#define CONFIG_AUTO_COMPLETE
821#define CONFIG_SYS_LOAD_ADDR 0x2000000
822#ifdef CONFIG_CMD_KGDB
823#define CONFIG_SYS_CBSIZE 1024
824#else
825#define CONFIG_SYS_CBSIZE 256
826#endif
827#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
828#define CONFIG_SYS_MAXARGS 16
829#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
830
831
832
833
834
835
836#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
837#define CONFIG_SYS_BOOTM_LEN (64 << 20)
838
839#ifdef CONFIG_CMD_KGDB
840#define CONFIG_KGDB_BAUDRATE 230400
841#endif
842
843
844
845
846#define CONFIG_ROOTPATH "/opt/nfsroot"
847#define CONFIG_BOOTFILE "uImage"
848#define CONFIG_UBOOTPATH u-boot.bin
849#define CONFIG_LOADADDR 1000000
850#define CONFIG_BAUDRATE 115200
851#define __USB_PHY_TYPE utmi
852
853#ifdef CONFIG_ARCH_T1024
854#define CONFIG_BOARDNAME t1024rdb
855#define BANK_INTLV cs0_cs1
856#else
857#define CONFIG_BOARDNAME t1023rdb
858#define BANK_INTLV null
859#endif
860
861#define CONFIG_EXTRA_ENV_SETTINGS \
862 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
863 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
864 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
865 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
866 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
867 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
868 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
869 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
870 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
871 "netdev=eth0\0" \
872 "tftpflash=tftpboot $loadaddr $uboot && " \
873 "protect off $ubootaddr +$filesize && " \
874 "erase $ubootaddr +$filesize && " \
875 "cp.b $loadaddr $ubootaddr $filesize && " \
876 "protect on $ubootaddr +$filesize && " \
877 "cmp.b $loadaddr $ubootaddr $filesize\0" \
878 "consoledev=ttyS0\0" \
879 "ramdiskaddr=2000000\0" \
880 "fdtaddr=1e00000\0" \
881 "bdev=sda3\0"
882
883#define CONFIG_LINUX \
884 "setenv bootargs root=/dev/ram rw " \
885 "console=$consoledev,$baudrate $othbootargs;" \
886 "setenv ramdiskaddr 0x02000000;" \
887 "setenv fdtaddr 0x00c00000;" \
888 "setenv loadaddr 0x1000000;" \
889 "bootm $loadaddr $ramdiskaddr $fdtaddr"
890
891#define CONFIG_NFSBOOTCOMMAND \
892 "setenv bootargs root=/dev/nfs rw " \
893 "nfsroot=$serverip:$rootpath " \
894 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr - $fdtaddr"
899
900#define CONFIG_BOOTCOMMAND CONFIG_LINUX
901
902
903#ifdef CONFIG_FSL_CAAM
904#define CONFIG_CMD_HASH
905#define CONFIG_SHA_HW_ACCEL
906#endif
907
908#include <asm/fsl_secure_boot.h>
909
910#endif
911