1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 29 30#define CONFIG_BOOTCOUNT_LIMIT 31 32 33#define CONFIG_BOARD_TYPES 1 /* support board types */ 34 35#define CONFIG_PREBOOT "echo;" \ 36 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 37 "echo" 38 39#undef CONFIG_BOOTARGS 40 41#define CONFIG_EXTRA_ENV_SETTINGS \ 42 "netdev=eth0\0" \ 43 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 44 "nfsroot=${serverip}:${rootpath}\0" \ 45 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 46 "addip=setenv bootargs ${bootargs} " \ 47 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 48 ":${hostname}:${netdev}:off panic=1\0" \ 49 "flash_nfs=run nfsargs addip;" \ 50 "bootm ${kernel_addr}\0" \ 51 "flash_self=run ramargs addip;" \ 52 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 53 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 54 "rootpath=/opt/eldk/ppc_8xx\0" \ 55 "hostname=TQM855M\0" \ 56 "bootfile=TQM855M/uImage\0" \ 57 "fdt_addr=40080000\0" \ 58 "kernel_addr=400A0000\0" \ 59 "ramdisk_addr=40280000\0" \ 60 "u-boot=TQM855M/u-image.bin\0" \ 61 "load=tftp 200000 ${u-boot}\0" \ 62 "update=prot off 40000000 +${filesize};" \ 63 "era 40000000 +${filesize};" \ 64 "cp.b 200000 40000000 ${filesize};" \ 65 "sete filesize;save\0" \ 66 "" 67#define CONFIG_BOOTCOMMAND "run flash_self" 68 69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 70#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 71 72#undef CONFIG_WATCHDOG /* watchdog disabled */ 73 74#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 75 76#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 77 78/* enable I2C and select the hardware/software driver */ 79#define CONFIG_SYS_I2C 80#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 81#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 82#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 83/* 84 * Software (bit-bang) I2C driver configuration 85 */ 86#define PB_SCL 0x00000020 /* PB 26 */ 87#define PB_SDA 0x00000010 /* PB 27 */ 88 89#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 90#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 91#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 92#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 93#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 94 else immr->im_cpm.cp_pbdat &= ~PB_SDA 95#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 96 else immr->im_cpm.cp_pbdat &= ~PB_SCL 97#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 98 99#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ 100#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 101#if 0 102#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 103#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 104#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 105#endif 106 107/* 108 * BOOTP options 109 */ 110#define CONFIG_BOOTP_SUBNETMASK 111#define CONFIG_BOOTP_GATEWAY 112#define CONFIG_BOOTP_HOSTNAME 113#define CONFIG_BOOTP_BOOTPATH 114#define CONFIG_BOOTP_BOOTFILESIZE 115 116#define CONFIG_MAC_PARTITION 117#define CONFIG_DOS_PARTITION 118 119#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 120 121/* 122 * Command line configuration. 123 */ 124#define CONFIG_CMD_DATE 125#define CONFIG_CMD_EEPROM 126#define CONFIG_CMD_IDE 127#define CONFIG_CMD_JFFS2 128 129#define CONFIG_NETCONSOLE 130 131/* 132 * Miscellaneous configurable options 133 */ 134#define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 136#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 137 138#if defined(CONFIG_CMD_KGDB) 139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 140#else 141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 142#endif 143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 146 147#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 148#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 149 150#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 151 152/* 153 * Low Level Configuration Settings 154 * (address mappings, register initial values, etc.) 155 * You should know what you are doing if you make changes here. 156 */ 157/*----------------------------------------------------------------------- 158 * Internal Memory Mapped Register 159 */ 160#define CONFIG_SYS_IMMR 0xFFF00000 161 162/*----------------------------------------------------------------------- 163 * Definitions for initial stack pointer and data area (in DPRAM) 164 */ 165#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 166#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 167#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 168#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 169 170/*----------------------------------------------------------------------- 171 * Start addresses for the final memory configuration 172 * (Set up by the startup code) 173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 174 */ 175#define CONFIG_SYS_SDRAM_BASE 0x00000000 176#define CONFIG_SYS_FLASH_BASE 0x40000000 177#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 179#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 180 181/* 182 * For booting Linux, the board info and command line data 183 * have to be in the first 8 MB of memory, since this is 184 * the maximum mapped by the Linux kernel during initialization. 185 */ 186#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 187 188/*----------------------------------------------------------------------- 189 * FLASH organization 190 */ 191 192/* use CFI flash driver */ 193#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 194#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 195#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 196#define CONFIG_SYS_FLASH_EMPTY_INFO 197#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 198#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 199#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 200 201#define CONFIG_ENV_IS_IN_FLASH 1 202#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 203#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 204#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 205 206/* Address and size of Redundant Environment Sector */ 207#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 208#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 209 210#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 211 212#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 213 214/*----------------------------------------------------------------------- 215 * Dynamic MTD partition support 216 */ 217#define CONFIG_CMD_MTDPARTS 218#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 219#define CONFIG_FLASH_CFI_MTD 220#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 221 222#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 223 "128k(dtb)," \ 224 "1920k(kernel)," \ 225 "5632(rootfs)," \ 226 "4m(data)" 227 228/*----------------------------------------------------------------------- 229 * Hardware Information Block 230 */ 231#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 232#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 233#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 234 235/*----------------------------------------------------------------------- 236 * Cache Configuration 237 */ 238#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 239#if defined(CONFIG_CMD_KGDB) 240#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 241#endif 242 243/*----------------------------------------------------------------------- 244 * SYPCR - System Protection Control 11-9 245 * SYPCR can only be written once after reset! 246 *----------------------------------------------------------------------- 247 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 248 */ 249#if defined(CONFIG_WATCHDOG) 250#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 251 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 252#else 253#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 254#endif 255 256/*----------------------------------------------------------------------- 257 * SIUMCR - SIU Module Configuration 11-6 258 *----------------------------------------------------------------------- 259 * PCMCIA config., multi-function pin tri-state 260 */ 261#ifndef CONFIG_CAN_DRIVER 262#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 263#else /* we must activate GPL5 in the SIUMCR for CAN */ 264#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 265#endif /* CONFIG_CAN_DRIVER */ 266 267/*----------------------------------------------------------------------- 268 * TBSCR - Time Base Status and Control 11-26 269 *----------------------------------------------------------------------- 270 * Clear Reference Interrupt Status, Timebase freezing enabled 271 */ 272#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 273 274/*----------------------------------------------------------------------- 275 * RTCSC - Real-Time Clock Status and Control Register 11-27 276 *----------------------------------------------------------------------- 277 */ 278#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 279 280/*----------------------------------------------------------------------- 281 * PISCR - Periodic Interrupt Status and Control 11-31 282 *----------------------------------------------------------------------- 283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 284 */ 285#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 286 287/*----------------------------------------------------------------------- 288 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 289 *----------------------------------------------------------------------- 290 * Reset PLL lock status sticky bit, timer expired status bit and timer 291 * interrupt status bit 292 */ 293#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 294 295/*----------------------------------------------------------------------- 296 * SCCR - System Clock and reset Control Register 15-27 297 *----------------------------------------------------------------------- 298 * Set clock output, timebase and RTC source and divider, 299 * power management and some other internal clocks 300 */ 301#define SCCR_MASK SCCR_EBDF11 302#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 303 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 304 SCCR_DFALCD00) 305 306/*----------------------------------------------------------------------- 307 * PCMCIA stuff 308 *----------------------------------------------------------------------- 309 * 310 */ 311#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 312#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 313#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 314#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 315#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 316#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 317#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 318#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 319 320/*----------------------------------------------------------------------- 321 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 322 *----------------------------------------------------------------------- 323 */ 324 325#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 326#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 327 328#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 329#undef CONFIG_IDE_LED /* LED for ide not supported */ 330#undef CONFIG_IDE_RESET /* reset for ide not supported */ 331 332#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 333#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 334 335#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 336 337#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 338 339/* Offset for data I/O */ 340#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 341 342/* Offset for normal register accesses */ 343#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 344 345/* Offset for alternate registers */ 346#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 347 348/*----------------------------------------------------------------------- 349 * 350 *----------------------------------------------------------------------- 351 * 352 */ 353#define CONFIG_SYS_DER 0 354 355/* 356 * Init Memory Controller: 357 * 358 * BR0/1 and OR0/1 (FLASH) 359 */ 360 361#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 362#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 363 364/* used to re-map FLASH both when starting from SRAM or FLASH: 365 * restrict access enough to keep SRAM working (if any) 366 * but not too much to meddle with FLASH accesses 367 */ 368#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 369#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 370 371/* 372 * FLASH timing: 373 */ 374#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 375 OR_SCY_3_CLK | OR_EHTR | OR_BI) 376 377#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 378#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 379#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 380 381#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 382#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 383#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 384 385/* 386 * BR2/3 and OR2/3 (SDRAM) 387 * 388 */ 389#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 390#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 391#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 392 393/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 394#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 395 396#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 397#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 398 399#ifndef CONFIG_CAN_DRIVER 400#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 401#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 402#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 403#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 404#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 405#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 406#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 407 BR_PS_8 | BR_MS_UPMB | BR_V ) 408#endif /* CONFIG_CAN_DRIVER */ 409 410/* 411 * Memory Periodic Timer Prescaler 412 * 413 * The Divider for PTA (refresh timer) configuration is based on an 414 * example SDRAM configuration (64 MBit, one bank). The adjustment to 415 * the number of chip selects (NCS) and the actually needed refresh 416 * rate is done by setting MPTPR. 417 * 418 * PTA is calculated from 419 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 420 * 421 * gclk CPU clock (not bus clock!) 422 * Trefresh Refresh cycle * 4 (four word bursts used) 423 * 424 * 4096 Rows from SDRAM example configuration 425 * 1000 factor s -> ms 426 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 427 * 4 Number of refresh cycles per period 428 * 64 Refresh cycle in ms per number of rows 429 * -------------------------------------------- 430 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 431 * 432 * 50 MHz => 50.000.000 / Divider = 98 433 * 66 Mhz => 66.000.000 / Divider = 129 434 * 80 Mhz => 80.000.000 / Divider = 156 435 */ 436 437#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 438#define CONFIG_SYS_MAMR_PTA 98 439 440/* 441 * For 16 MBit, refresh rates could be 31.3 us 442 * (= 64 ms / 2K = 125 / quad bursts). 443 * For a simpler initialization, 15.6 us is used instead. 444 * 445 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 446 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 447 */ 448#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 449#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 450 451/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 452#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 453#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 454 455/* 456 * MAMR settings for SDRAM 457 */ 458 459/* 8 column SDRAM */ 460#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 461 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 462 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 463/* 9 column SDRAM */ 464#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 465 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 467 468#define CONFIG_SCC1_ENET 469#define CONFIG_FEC_ENET 470#define CONFIG_ETHPRIME "SCC" 471 472#define CONFIG_HWCONFIG 1 473 474#endif /* __CONFIG_H */ 475