1/* 2 * Copyright (C) 2006 Atmel Corporation 3 * 4 * Configuration settings for the AVR32 Network Gateway 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11#include <asm/arch/hardware.h> 12 13#define CONFIG_AT32AP 14#define CONFIG_AT32AP7000 15#define CONFIG_ATNGW100 16 17#define CONFIG_BOARD_EARLY_INIT_F 18#define CONFIG_BOARD_EARLY_INIT_R 19 20/* 21 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 22 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency 23 * and the PBA bus to run at 1/4 the PLL frequency. 24 */ 25#define CONFIG_PLL 26#define CONFIG_SYS_POWER_MANAGER 27#define CONFIG_SYS_OSC0_HZ 20000000 28#define CONFIG_SYS_PLL0_DIV 1 29#define CONFIG_SYS_PLL0_MUL 7 30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 31#define CONFIG_SYS_CLKDIV_CPU 0 32#define CONFIG_SYS_CLKDIV_HSB 1 33#define CONFIG_SYS_CLKDIV_PBA 2 34#define CONFIG_SYS_CLKDIV_PBB 1 35 36/* Reserve VM regions for SDRAM and NOR flash */ 37#define CONFIG_SYS_NR_VM_REGIONS 2 38 39/* 40 * The PLLOPT register controls the PLL like this: 41 * icp = PLLOPT<2> 42 * ivco = PLLOPT<1:0> 43 * 44 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 45 */ 46#define CONFIG_SYS_PLL0_OPT 0x04 47 48#define CONFIG_USART_BASE ATMEL_BASE_USART1 49#define CONFIG_USART_ID 1 50/* User serviceable stuff */ 51#define CONFIG_DOS_PARTITION 52 53#define CONFIG_CMDLINE_TAG 54#define CONFIG_SETUP_MEMORY_TAGS 55#define CONFIG_INITRD_TAG 56 57#define CONFIG_STACKSIZE (2048) 58 59#define CONFIG_BAUDRATE 115200 60#define CONFIG_BOOTARGS \ 61 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" 62#define CONFIG_BOOTCOMMAND \ 63 "fsload; bootm" 64 65 66/* 67 * After booting the board for the first time, new ethernet addresses 68 * should be generated and assigned to the environment variables 69 * "ethaddr" and "eth1addr". This is normally done during production. 70 */ 71#define CONFIG_OVERWRITE_ETHADDR_ONCE 72 73/* 74 * BOOTP/DHCP options 75 */ 76#define CONFIG_BOOTP_SUBNETMASK 77#define CONFIG_BOOTP_GATEWAY 78 79/* 80 * Command line configuration. 81 */ 82#define CONFIG_CMD_JFFS2 83 84#define CONFIG_ATMEL_USART 85#define CONFIG_MACB 86#define CONFIG_PORTMUX_PIO 87#define CONFIG_SYS_NR_PIOS 5 88#define CONFIG_SYS_HSDRAMC 89#define CONFIG_GENERIC_ATMEL_MCI 90#define CONFIG_GENERIC_MMC 91#define CONFIG_ATMEL_SPI 92 93#define CONFIG_SYS_DCACHE_LINESZ 32 94#define CONFIG_SYS_ICACHE_LINESZ 32 95 96#define CONFIG_NR_DRAM_BANKS 1 97 98#define CONFIG_SYS_FLASH_CFI 99#define CONFIG_FLASH_CFI_DRIVER 100 101#define CONFIG_SYS_FLASH_BASE 0x00000000 102#define CONFIG_SYS_FLASH_SIZE 0x800000 103#define CONFIG_SYS_MAX_FLASH_BANKS 1 104#define CONFIG_SYS_MAX_FLASH_SECT 135 105 106#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 107#define CONFIG_SYS_TEXT_BASE 0x00000000 108 109#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 110#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 111#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 112 113#define CONFIG_ENV_IS_IN_FLASH 114#define CONFIG_ENV_SIZE 65536 115#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 116 117#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 118 119#define CONFIG_SYS_MALLOC_LEN (256*1024) 120 121/* Allow 4MB for the kernel run-time image */ 122#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 123#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 124 125/* Other configuration settings that shouldn't have to change all that often */ 126#define CONFIG_SYS_CBSIZE 256 127#define CONFIG_SYS_MAXARGS 16 128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 129#define CONFIG_SYS_LONGHELP 130 131#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 132#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) 133 134#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 135 136#endif /* __CONFIG_H */ 137