1/* 2 * U-Boot - Configuration file for BF561 EZKIT board 3 */ 4 5#ifndef __CONFIG_BF561_EZKIT_H__ 6#define __CONFIG_BF561_EZKIT_H__ 7 8#include <asm/config-pre.h> 9 10/* 11 * Processor Settings 12 */ 13#define CONFIG_BFIN_CPU bf561-0.3 14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 15 16/* 17 * Clock Settings 18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 20 */ 21/* CONFIG_CLKIN_HZ is any value in Hz */ 22#define CONFIG_CLKIN_HZ 30000000 23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 24/* 1 = CLKIN / 2 */ 25#define CONFIG_CLKIN_HALF 0 26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 27/* 1 = bypass PLL */ 28#define CONFIG_PLL_BYPASS 0 29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 30/* Values can range from 0-63 (where 0 means 64) */ 31#define CONFIG_VCO_MULT 20 32/* CCLK_DIV controls the core clock divider */ 33/* Values can be 1, 2, 4, or 8 ONLY */ 34#define CONFIG_CCLK_DIV 1 35/* SCLK_DIV controls the system clock divider */ 36/* Values can range from 1-15 */ 37#define CONFIG_SCLK_DIV 6 38 39/* 40 * Memory Settings 41 */ 42#define CONFIG_MEM_ADD_WDTH 9 43#define CONFIG_MEM_SIZE 64 44 45#define CONFIG_EBIU_SDRRC_VAL 0x306 46#define CONFIG_EBIU_SDGCTL_VAL 0x91114d 47 48#define CONFIG_EBIU_AMGCTL_VAL 0x3F 49#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 50#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 51 52#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 53#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 54 55/* 56 * Network Settings 57 */ 58#define ADI_CMDS_NETWORK 1 59#define CONFIG_SMC91111 1 60#define CONFIG_SMC91111_BASE 0x2C010300 61#define CONFIG_SMC_USE_32_BIT 1 62#define CONFIG_HOSTNAME bf561-ezkit 63 64/* 65 * Flash Settings 66 */ 67#define CONFIG_SYS_FLASH_CFI 68#define CONFIG_FLASH_CFI_DRIVER 69#define CONFIG_SYS_FLASH_CFI_AMD_RESET 70#define CONFIG_SYS_FLASH_BASE 0x20000000 71#define CONFIG_SYS_MAX_FLASH_BANKS 1 72#define CONFIG_SYS_MAX_FLASH_SECT 135 73/* The BF561-EZKIT uses a top boot flash */ 74#define CONFIG_ENV_IS_IN_FLASH 1 75#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE) 76#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 77#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 78#define CONFIG_ENV_SECT_SIZE 0x2000 79 80/* 81 * I2C Settings 82 */ 83#define CONFIG_SYS_I2C_SOFT 84#ifdef CONFIG_SYS_I2C_SOFT 85#define CONFIG_SYS_I2C 86#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 87#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 88#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 89#define CONFIG_SYS_I2C_SOFT_SPEED 50000 90#define CONFIG_SYS_I2C_SOFT_SLAVE 0 91#endif 92 93/* 94 * Misc Settings 95 */ 96#define CONFIG_UART_CONSOLE 0 97 98/* 99 * Run core 1 from L1 SRAM start address when init uboot on core 0 100 */ 101/* #define CONFIG_CORE1_RUN 1 */ 102 103/* 104 * Pull in common ADI header for remaining command/environment setup 105 */ 106#include <configs/bfin_adi_common.h> 107 108#endif 109