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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_IOCON 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME iocon
20#include "amcc-common.h"
21
22
23#undef CONFIG_SYS_LONGHELP
24
25#define CONFIG_BOARD_EARLY_INIT_F
26#define CONFIG_BOARD_EARLY_INIT_R
27#define CONFIG_LAST_STAGE_INIT
28
29#define CONFIG_SYS_CLK_FREQ 33333333
30
31
32
33
34#define PLLMR0_DEFAULT PLLMR0_266_133_66
35#define PLLMR1_DEFAULT PLLMR1_266_133_66
36
37
38#define CONFIG_FIT_DISABLE_SHA256
39
40#define CONFIG_ENV_IS_IN_FLASH
41
42
43
44
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 CONFIG_AMCC_DEF_ENV \
47 CONFIG_AMCC_DEF_ENV_POWERPC \
48 CONFIG_AMCC_DEF_ENV_NOR_UPD \
49 "kernel_addr=fc000000\0" \
50 "fdt_addr=fc1e0000\0" \
51 "ramdisk_addr=fc200000\0" \
52 ""
53
54#define CONFIG_PHY_ADDR 4
55#define CONFIG_HAS_ETH0
56#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
57
58
59
60
61#define CONFIG_CMD_FPGAD
62#undef CONFIG_CMD_EEPROM
63#undef CONFIG_CMD_IRQ
64
65
66
67
68#define CONFIG_SDRAM_BANK0 1
69
70
71#define CONFIG_SYS_SDRAM_CL 3
72#define CONFIG_SYS_SDRAM_tRP 20
73#define CONFIG_SYS_SDRAM_tRC 66
74#define CONFIG_SYS_SDRAM_tRCD 20
75#define CONFIG_SYS_SDRAM_tRFC 66
76
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83
84
85
86#define CONFIG_CONS_INDEX 1
87#undef CONFIG_SYS_EXT_SERIAL_CLOCK
88#undef CONFIG_SYS_405_UART_ERRATA_59
89#define CONFIG_SYS_BASE_BAUD 691200
90
91
92
93
94#define CONFIG_SYS_I2C
95#define CONFIG_SYS_I2C_PPC4XX
96#define CONFIG_SYS_I2C_PPC4XX_CH0
97#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
98#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
99#define CONFIG_SYS_I2C_IHS
100
101#define CONFIG_SYS_I2C_SPEED 400000
102#define CONFIG_SYS_SPD_BUS_NUM 4
103
104#define CONFIG_PCA953X
105#define CONFIG_PCA9698
106
107#define CONFIG_SYS_I2C_IHS_CH0
108#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
109#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
110#define CONFIG_SYS_I2C_IHS_CH1
111#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
112#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
113#define CONFIG_SYS_I2C_IHS_CH2
114#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
115#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
116#define CONFIG_SYS_I2C_IHS_CH3
117#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
118#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
119
120
121
122
123#define CONFIG_SYS_I2C_SOFT
124#define CONFIG_SYS_I2C_SOFT_SPEED 50000
125#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
126#define I2C_SOFT_DECLARATIONS2
127#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
128#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
129#define I2C_SOFT_DECLARATIONS3
130#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
131#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
132#define I2C_SOFT_DECLARATIONS4
133#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
134#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
135
136#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
137#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
138#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
139
140#ifndef __ASSEMBLY__
141void fpga_gpio_set(unsigned int bus, int pin);
142void fpga_gpio_clear(unsigned int bus, int pin);
143int fpga_gpio_get(unsigned int bus, int pin);
144#endif
145
146#define I2C_ACTIVE { }
147#define I2C_TRISTATE { }
148#define I2C_READ \
149 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
150#define I2C_SDA(bit) \
151 do { \
152 if (bit) \
153 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
154 else \
155 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
156 } while (0)
157#define I2C_SCL(bit) \
158 do { \
159 if (bit) \
160 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
161 else \
162 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
163 } while (0)
164#define I2C_DELAY udelay(25)
165
166
167
168
169#define CONFIG_SYS_FLASH_CFI
170#define CONFIG_FLASH_CFI_DRIVER
171
172#define CONFIG_SYS_FLASH_BASE 0xFC000000
173#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
174
175#define CONFIG_SYS_MAX_FLASH_BANKS 1
176#define CONFIG_SYS_MAX_FLASH_SECT 512
177
178#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
179#define CONFIG_SYS_FLASH_WRITE_TOUT 500
180
181#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
182
183#define CONFIG_SYS_FLASH_EMPTY_INFO
184#define CONFIG_SYS_FLASH_QUIET_TEST 1
185
186#ifdef CONFIG_ENV_IS_IN_FLASH
187#define CONFIG_ENV_SECT_SIZE 0x20000
188#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE 0x2000
190
191
192#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
193#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
194#endif
195
196
197
198
199#define CONFIG_SYS_4xx_GPIO_TABLE { \
200{ \
201 \
202{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
207{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
208{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
211{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
213{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
215{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
219{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
220{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
221{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
222{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
223{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
224{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
225{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
226{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
227{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
228{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
229{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
230{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
231{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
232{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
233{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
234} \
235}
236
237
238
239
240
241#define CONFIG_SYS_TEMP_STACK_OCM 1
242
243
244#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
245#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
246#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
247#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
248
249#define CONFIG_SYS_GBL_DATA_OFFSET \
250 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
251#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
252
253
254
255
256
257
258#define CONFIG_SYS_EBC_PB0AP 0xa382a880
259#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
260
261
262#define CONFIG_SYS_EBC_PB1AP 0x92015480
263#define CONFIG_SYS_EBC_PB1CR 0xFB858000
264
265
266#define CONFIG_SYS_FPGA0_BASE 0x7f100000
267#define CONFIG_SYS_EBC_PB2AP 0x02825080
268#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
269
270#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
271#define CONFIG_SYS_FPGA_DONE(k) 0x0010
272
273#define CONFIG_SYS_FPGA_COUNT 1
274
275#define CONFIG_SYS_MCLINK_MAX 3
276
277#define CONFIG_SYS_FPGA_PTR \
278 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
279
280
281#define CONFIG_SYS_LATCH_BASE 0x7f200000
282#define CONFIG_SYS_EBC_PB3AP 0x02025080
283#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
284
285#define CONFIG_SYS_LATCH0_RESET 0xffef
286#define CONFIG_SYS_LATCH0_BOOT 0xffff
287#define CONFIG_SYS_LATCH1_RESET 0xffff
288#define CONFIG_SYS_LATCH1_BOOT 0xffff
289
290
291
292
293#define CONFIG_SYS_MPC92469AC
294#define CONFIG_SYS_OSD_SCREENS 1
295#define CONFIG_SYS_DP501_DIFFERENTIAL
296#define CONFIG_SYS_DP501_VCAPCTRL0 0x01
297
298#define CONFIG_BITBANGMII
299#define CONFIG_BITBANGMII_MULTI
300
301#endif
302