1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21#define CONFIG_MAKALU 1
22#define CONFIG_405EX 1
23#define CONFIG_SYS_CLK_FREQ 33330000
24
25#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
26
27
28
29
30#define CONFIG_HOSTNAME makalu
31#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
32#include "amcc-common.h"
33
34#define CONFIG_BOARD_EARLY_INIT_F 1
35#define CONFIG_MISC_INIT_R 1
36
37
38
39
40
41#define CONFIG_SYS_FLASH_BASE 0xFC000000
42#define CONFIG_SYS_FPGA_BASE 0xF0000000
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66#define CONFIG_SYS_INIT_DCACHE_CS 4
67
68#if defined(CONFIG_SYS_INIT_DCACHE_CS)
69#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))
70#else
71#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20))
72#endif
73
74#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
75#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
76
77
78
79
80
81
82
83
84
85#if defined(CONFIG_SYS_INIT_DCACHE_CS)
86# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
87# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
88#else
89# define CONFIG_SYS_INIT_EXTRA_SIZE 16
90# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
91# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
92#endif
93
94
95
96
97#define CONFIG_CONS_INDEX 1
98#undef CONFIG_SYS_EXT_SERIAL_CLOCK
99
100
101
102
103#define CONFIG_ENV_IS_IN_FLASH 1
104
105
106
107
108#define CONFIG_SYS_FLASH_CFI
109#define CONFIG_FLASH_CFI_DRIVER
110
111#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
112#define CONFIG_SYS_MAX_FLASH_BANKS 1
113#define CONFIG_SYS_MAX_FLASH_SECT 512
114
115#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
116#define CONFIG_SYS_FLASH_WRITE_TOUT 500
117
118#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
119#define CONFIG_SYS_FLASH_EMPTY_INFO
120
121#ifdef CONFIG_ENV_IS_IN_FLASH
122#define CONFIG_ENV_SECT_SIZE 0x20000
123#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
124#define CONFIG_ENV_SIZE 0x4000
125
126
127#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
128#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
129#endif
130
131
132
133
134#define CONFIG_SYS_MBYTES_SDRAM (256)
135
136#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
137#define CONFIG_SYS_SDRAM0_MB1CF_BASE ((128 << 20) + CONFIG_SYS_SDRAM_BASE)
138
139
140#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
141 SDRAM_RXBAS_SDSZ_128MB | \
142 SDRAM_RXBAS_SDAM_MODE2 | \
143 SDRAM_RXBAS_SDBE_ENABLE)
144#define CONFIG_SYS_SDRAM0_MB1CF ((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3) | \
145 SDRAM_RXBAS_SDSZ_128MB | \
146 SDRAM_RXBAS_SDAM_MODE2 | \
147 SDRAM_RXBAS_SDBE_ENABLE)
148#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
149#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
150#define CONFIG_SYS_SDRAM0_MCOPT1 0x04322000
151#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
152#define CONFIG_SYS_SDRAM0_MODT0 0x01800000
153#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
154#define CONFIG_SYS_SDRAM0_CODT 0x0080f837
155#define CONFIG_SYS_SDRAM0_RTR 0x06180000
156#define CONFIG_SYS_SDRAM0_INITPLR0 0xa8380000
157#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
158#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
159#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
160#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010404
161#define CONFIG_SYS_SDRAM0_INITPLR5 0x81000542
162#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
163#define CONFIG_SYS_SDRAM0_INITPLR7 0x8D080000
164#define CONFIG_SYS_SDRAM0_INITPLR8 0x8D080000
165#define CONFIG_SYS_SDRAM0_INITPLR9 0x8D080000
166#define CONFIG_SYS_SDRAM0_INITPLR10 0x8D080000
167#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
168#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010780
169#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010400
170#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
171#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
172#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
173#define CONFIG_SYS_SDRAM0_RFDC 0x00000209
174#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
175#define CONFIG_SYS_SDRAM0_DLCR 0x030000a5
176#define CONFIG_SYS_SDRAM0_CLKTR 0x80000000
177#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
178#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
179#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
180#define CONFIG_SYS_SDRAM0_SDTR3 0x080b0d1a
181#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
182#define CONFIG_SYS_SDRAM0_MEMODE 0x00000404
183
184
185
186
187#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
188
189#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6
190#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
191#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
192
193
194#define CONFIG_DTT_DS1775 1
195#define CONFIG_DTT_SENSORS { 0 }
196#define CONFIG_SYS_I2C_DTT_ADDR 0x48
197
198
199#define CONFIG_RTC_X1205 1
200#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
201
202
203
204
205#define CONFIG_M88E1111_PHY 1
206#define CONFIG_IBM_EMAC4_V4 1
207#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
208#define CONFIG_PHY_ADDR 6
209
210#define CONFIG_PHY_RESET 1
211#define CONFIG_PHY_GIGE 1
212
213#define CONFIG_HAS_ETH0 1
214
215#define CONFIG_HAS_ETH1 1
216#define CONFIG_PHY1_ADDR 0
217
218
219
220
221#define CONFIG_EXTRA_ENV_SETTINGS \
222 CONFIG_AMCC_DEF_ENV \
223 CONFIG_AMCC_DEF_ENV_POWERPC \
224 CONFIG_AMCC_DEF_ENV_PPC_OLD \
225 CONFIG_AMCC_DEF_ENV_NOR_UPD \
226 "kernel_addr=fc000000\0" \
227 "fdt_addr=fc1e0000\0" \
228 "ramdisk_addr=fc200000\0" \
229 "pciconfighost=1\0" \
230 "pcie_mode=RP:RP\0" \
231 ""
232
233
234
235
236#define CONFIG_CMD_DATE
237#define CONFIG_CMD_DTT
238#define CONFIG_CMD_PCI
239
240
241#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
242 CONFIG_SYS_POST_CPU | \
243 CONFIG_SYS_POST_ETHER | \
244 CONFIG_SYS_POST_I2C | \
245 CONFIG_SYS_POST_MEMORY | \
246 CONFIG_SYS_POST_UART)
247
248
249#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
250 CONFIG_SYS_NS16550_COM2 }
251
252#define CONFIG_LOGBUFFER
253#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000
254
255
256
257
258#define CONFIG_PCI_INDIRECT_BRIDGE
259#define CONFIG_PCI_SCAN_SHOW 1
260#define CONFIG_PCI_CONFIG_HOST_BRIDGE
261
262
263
264
265#define CONFIG_SYS_PCIE_MEMBASE 0x90000000
266#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000
267
268#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000
269#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
270#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001
271
272#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000
273#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000
274#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001
275
276#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
277#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
278
279
280#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
281
282
283
284
285
286#define CONFIG_SYS_EBC_PB0AP 0x08033700
287#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
288
289
290#define CONFIG_SYS_EBC_PB2AP 0x9400C800
291#define CONFIG_SYS_EBC_PB2CR 0xF0018000
292
293#define CONFIG_SYS_EBC_CFG 0x7FC00000
294
295
296
297
298#define CONFIG_SYS_4xx_GPIO_TABLE { \
299{ \
300 \
301{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
302{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
303{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
304{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
305{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
306{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
307{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
308{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
309{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
310{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
311{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
312{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
313{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
314{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
315{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
316{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, \
317{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
318{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
319{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, \
320{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
321{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
322{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
323{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
324{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, \
325{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
326{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
327{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
328{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, \
329{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, \
330{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
331{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
332{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, \
333} \
334}
335
336#define CONFIG_SYS_GPIO_PCIE_RST 23
337#define CONFIG_SYS_GPIO_PCIE_CLKREQ 27
338#define CONFIG_SYS_GPIO_PCIE_WAKE 28
339
340#endif
341