1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2006 6 * Eric Schumann, Phytec Messatechnik GmbH 7 * 8 * (C) Copyright 2009 9 * Jon Smirl <jonsmirl@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#ifndef __CONFIG_H 15#define __CONFIG_H 16 17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" 18 19/*----------------------------------------------------------------------------- 20High Level Configuration Options 21(easy to change) 22-----------------------------------------------------------------------------*/ 23#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ 24#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ 25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ 26 /* FEC configuration and IDE */ 27 28/* 29 * Valid values for CONFIG_SYS_TEXT_BASE are: 30 * 0xFFF00000 boot high (standard configuration) 31 * 0xFF000000 boot low 32 * 0x00100000 boot from RAM (for testing only) 33 */ 34#ifndef CONFIG_SYS_TEXT_BASE 35#define CONFIG_SYS_TEXT_BASE 0xFFF00000 36#endif 37 38#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ 39 40/*----------------------------------------------------------------------------- 41Serial console configuration 42-----------------------------------------------------------------------------*/ 43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ 44 /*define gps port conf. */ 45 /* register later on to */ 46 /*enable UART function! */ 47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 49 50/* 51 * Command line configuration. 52 */ 53#define CONFIG_CMD_DATE 54#define CONFIG_CMD_EEPROM 55#define CONFIG_CMD_JFFS2 56#define CONFIG_CMD_PCI 57 58#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ 59 60#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */ 61#define CONFIG_SYS_LOWBOOT 1 62#endif 63/* RAMBOOT will be defined automatically in memory section */ 64 65#define CONFIG_JFFS2_CMDLINE 66#define MTDIDS_DEFAULT "nor0=physmap-flash.0" 67#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ 68 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" 69 70#undef CONFIG_BOOTARGS 71 72#define CONFIG_PREBOOT "echo;" \ 73 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ 74 "mount root filesystem over NFS;" \ 75 "echo" 76 77#define CONFIG_EXTRA_ENV_SETTINGS \ 78 "netdev=eth0\0" \ 79 "uimage=uImage-pcm030\0" \ 80 "oftree=oftree-pcm030.dtb\0" \ 81 "jffs2=root-pcm030.jffs2\0" \ 82 "uboot=u-boot-pcm030.bin\0" \ 83 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ 84 " $(mtdparts) rw\0" \ 85 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ 86 " rootfstype=jffs2\0" \ 87 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ 88 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ 89 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 90 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ 91 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ 92 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ 93 "0xfff40000\0" \ 94 " cp.b 0x400000 0xff040000 $(filesize)\0" \ 95 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ 96 "cp.b 0x400000 0xff200000 $(filesize)\0" \ 97 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ 98 " cp.b 0x400000 0xfff40000 $(filesize)\0" \ 99 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ 100 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ 101 "unlock=yes\0" \ 102 "" 103 104#define CONFIG_BOOTCOMMAND "run bcmd_flash" 105 106/*-------------------------------------------------------------------------- 107IPB Bus clocking configuration. 108 ---------------------------------------------------------------------------*/ 109#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 110 111/*------------------------------------------------------------------------- 112 * PCI Mapping: 113 * 0x40000000 - 0x4fffffff - PCI Memory 114 * 0x50000000 - 0x50ffffff - PCI IO Space 115 * -----------------------------------------------------------------------*/ 116#define CONFIG_PCI_SCAN_SHOW 1 117#define CONFIG_PCI_MEM_BUS 0x40000000 118#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 119#define CONFIG_PCI_MEM_SIZE 0x10000000 120#define CONFIG_PCI_IO_BUS 0x50000000 121#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 122#define CONFIG_PCI_IO_SIZE 0x01000000 123#define CONFIG_SYS_XLB_PIPELINING 1 124 125/*--------------------------------------------------------------------------- 126 I2C configuration 127---------------------------------------------------------------------------*/ 128#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 129#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 130#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 131#define CONFIG_SYS_I2C_SLAVE 0x7F 132 133/*--------------------------------------------------------------------------- 134 EEPROM CAT24WC32 configuration 135---------------------------------------------------------------------------*/ 136#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ 137#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ 138#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 139#define CONFIG_SYS_EEPROM_SIZE 2048 140#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 141#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 142 143/*--------------------------------------------------------------------------- 144RTC configuration 145---------------------------------------------------------------------------*/ 146#define RTC 147#define CONFIG_RTC_PCF8563 1 148#define CONFIG_SYS_I2C_RTC_ADDR 0x51 149 150/*--------------------------------------------------------------------------- 151 Flash configuration 152---------------------------------------------------------------------------*/ 153 154#define CONFIG_SYS_FLASH_BASE 0xff000000 155#define CONFIG_SYS_FLASH_SIZE 0x01000000 156#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 157 158#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 159#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 160#define CONFIG_SYS_FLASH_EMPTY_INFO 161#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ 162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 163 /* (= chip selects) */ 164#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 165 166/* 167 * Use also hardware protection. This seems required, as the BDI uses 168 * hardware protection. Without this, U-Boot can't work with this sectors, 169 * as its protection is software only by default 170 */ 171#define CONFIG_SYS_FLASH_PROTECTION 1 172 173/*--------------------------------------------------------------------------- 174 Environment settings 175---------------------------------------------------------------------------*/ 176 177/* pcm030 ships with environment is EEPROM by default */ 178#define CONFIG_ENV_IS_IN_EEPROM 1 179#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ 180 /*beginning of the EEPROM */ 181#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE 182 183#define CONFIG_ENV_OVERWRITE 1 184 185/*----------------------------------------------------------------------------- 186 Memory map 187-----------------------------------------------------------------------------*/ 188#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ 189 /* bootloader or debugger config */ 190#define CONFIG_SYS_SDRAM_BASE 0x00000000 191#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 192/* Use SRAM until RAM will be available */ 193#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 194#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */ 195 /* area in DPRAM */ 196#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 197 GENERATED_GBL_DATA_SIZE) 198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 201#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 202# define CONFIG_SYS_RAMBOOT 1 203#endif 204 205#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 206#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 208 209/*----------------------------------------------------------------------------- 210 Ethernet configuration 211-----------------------------------------------------------------------------*/ 212#define CONFIG_MPC5xxx_FEC 1 213#define CONFIG_MPC5xxx_FEC_MII100 214#define CONFIG_PHY_ADDR 0x01 215 216/*--------------------------------------------------------------------------- 217 GPIO configuration 218 ---------------------------------------------------------------------------*/ 219 220/* GPIO port configuration 221 * 222 * Pin mapping: 223 * 224 * [29:31] = 01x 225 * PSC1_0 -> AC97 SDATA out 226 * PSC1_1 -> AC97 SDTA in 227 * PSC1_2 -> AC97 SYNC out 228 * PSC1_3 -> AC97 bitclock out 229 * PSC1_4 -> AC97 reset out 230 * 231 * [25:27] = 001 232 * PSC2_0 -> CAN 1 Tx out 233 * PSC2_1 -> CAN 1 Rx in 234 * PSC2_2 -> CAN 2 Tx out 235 * PSC2_3 -> CAN 2 Rx in 236 * PSC2_4 -> GPIO (claimed for ATA reset, active low) 237 * 238 * 239 * [20:23] = 1100 240 * PSC3_0 -> UART Tx out 241 * PSC3_1 -> UART Rx in 242 * PSC3_2 -> UART RTS (in/out FIXME) 243 * PSC3_3 -> UART CTS (in/out FIXME) 244 * PSC3_4 -> LocalPlus Bus CS6 \ 245 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] 246 * PSC3_6 -> dedicated SPI MOSI out (master case) 247 * PSC3_7 -> dedicated SPI MISO in (master case) 248 * PSC3_8 -> dedicated SPI SS out (master case) 249 * PSC3_9 -> dedicated SPI CLK out (master case) 250 * 251 * [18:19] = 01 252 * USB_0 -> USB OE out 253 * USB_1 -> USB Tx- out 254 * USB_2 -> USB Tx+ out 255 * USB_3 -> USB RxD (in/out FIXME) 256 * USB_4 -> USB Rx+ in 257 * USB_5 -> USB Rx- in 258 * USB_6 -> USB PortPower out 259 * USB_7 -> USB speed out 260 * USB_8 -> USB suspend (in/out FIXME) 261 * USB_9 -> USB overcurrent in 262 * 263 * [17] = 0 264 * USB differential mode 265 * 266 * [16] = 0 267 * PCI enabled 268 * 269 * [12:15] = 0101 270 * ETH_0 -> ETH Txen 271 * ETH_1 -> ETH TxD0 272 * ETH_2 -> ETH TxD1 273 * ETH_3 -> ETH TxD2 274 * ETH_4 -> ETH TxD3 275 * ETH_5 -> ETH Txerr 276 * ETH_6 -> ETH MDC 277 * ETH_7 -> ETH MDIO 278 * ETH_8 -> ETH RxDv 279 * ETH_9 -> ETH RxCLK 280 * ETH_10 -> ETH Collision 281 * ETH_11 -> ETH TxD 282 * ETH_12 -> ETH RxD0 283 * ETH_13 -> ETH RxD1 284 * ETH_14 -> ETH RxD2 285 * ETH_15 -> ETH RxD3 286 * ETH_16 -> ETH Rxerr 287 * ETH_17 -> ETH CRS 288 * 289 * [9:11] = 101 290 * PSC6_0 -> UART RxD in 291 * PSC6_1 -> UART CTS (in/out FIXME) 292 * PSC6_2 -> UART TxD out 293 * PSC6_3 -> UART RTS (in/out FIXME) 294 * 295 * [2:3/6:7] = 00/11 296 * TMR_0 -> ATA_CS0 out 297 * TMR_1 -> ATA_CS1 out 298 * TMR_2 -> GPIO 299 * TMR_3 -> GPIO 300 * TMR_4 -> GPIO 301 * TMR_5 -> GPIO 302 * TMR_6 -> GPIO 303 * TMR_7 -> GPIO 304 * I2C_0 -> I2C 1 Clock out 305 * I2C_1 -> I2C 1 IO in/out 306 * I2C_2 -> I2C 2 Clock out 307 * I2C_3 -> I2C 2 IO in/out 308 * 309 * [4] = 1 310 * PSC3_5 is used as CS7 311 * 312 * [5] = 1 313 * PSC3_4 is used as CS6 314 * 315 * [1] = 0 316 * gpio_wkup_7 is GPIO 317 * 318 * [0] = 0 319 * gpio_wkup_6 is GPIO 320 * 321 */ 322#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 323 324/*----------------------------------------------------------------------------- 325 Miscellaneous configurable options 326-------------------------------------------------------------------------------*/ 327#define CONFIG_SYS_LONGHELP /* undef to save memory */ 328 329#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 330 331#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 332#if defined(CONFIG_CMD_KGDB) 333#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 334#endif 335 336#if defined(CONFIG_CMD_KGDB) 337#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 338#else 339#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 340#endif 341#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 342 /* Print Buffer Size */ 343#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 344#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 345 346#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 347#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 348 349#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 350 351/*----------------------------------------------------------------------------- 352 Various low-level settings 353-----------------------------------------------------------------------------*/ 354#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 355#define CONFIG_SYS_HID0_FINAL HID0_ICE 356 357/* no burst access on the LPB */ 358#define CONFIG_SYS_CS_BURST 0x00000000 359/* one deadcycle for the 33MHz statemachine */ 360#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 361/* one additional waitstate for the 33MHz statemachine */ 362#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 363#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 364#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 365 366#define CONFIG_SYS_RESET_ADDRESS 0xff000000 367 368/*----------------------------------------------------------------------- 369 * USB stuff 370 *----------------------------------------------------------------------- 371 */ 372#define CONFIG_USB_CLOCK 0x0001BBBB 373#define CONFIG_USB_CONFIG 0x00001000 374 375/*--------------------------------------------------------------------------- 376 IDE/ATA stuff Supports IDE harddisk 377----------------------------------------------------------------------------*/ 378 379#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 380#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 381#undef CONFIG_IDE_LED /* LED for ide not supported */ 382#define CONFIG_SYS_ATA_CS_ON_TIMER01 383#define CONFIG_IDE_RESET 1 /* reset for ide supported */ 384#define CONFIG_IDE_PREINIT 385#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 386#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ 387#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 388#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 389/* Offset for data I/O */ 390#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 391/* Offset for normal register accesses */ 392#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 393/* Offset for alternate registers */ 394#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 395/* Interval between registers */ 396#define CONFIG_SYS_ATA_STRIDE 4 397#define CONFIG_ATAPI 1 398 399/* we enable IDE and FAT support, so we also need partition support */ 400#define CONFIG_DOS_PARTITION 1 401 402/* USB */ 403#define CONFIG_USB_OHCI 404 405/* pass open firmware flat tree */ 406#define OF_CPU "PowerPC,5200@0" 407#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN 408#define OF_SOC "soc5200@f0000000" 409#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" 410 411#endif /* __CONFIG_H */ 412