1/* 2 * Configuation settings for the Renesas RSK2+SH7264 board 3 * 4 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008 Renesas Solutions Corp. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#ifndef __RSK7264_H 12#define __RSK7264_H 13 14#define CONFIG_CPU_SH7264 1 15#define CONFIG_RSK7264 1 16 17#define CONFIG_DISPLAY_BOARDINFO 18 19#define CONFIG_BAUDRATE 115200 20#define CONFIG_BOOTARGS "console=ttySC3,115200" 21#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 22 23#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 24#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 25#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 26#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 27 28/* Serial */ 29#define CONFIG_SCIF_CONSOLE 1 30#define CONFIG_CONS_SCIF3 1 31 32/* Memory */ 33/* u-boot relocated to top 256KB of ram */ 34#define CONFIG_SYS_TEXT_BASE 0x0CFC0000 35#define CONFIG_SYS_SDRAM_BASE 0x0C000000 36#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 37 38#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 39#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 40#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 41#define CONFIG_SYS_MONITOR_LEN (128 * 1024) 42#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 43 44/* Flash */ 45#define CONFIG_FLASH_CFI_DRIVER 46#define CONFIG_SYS_FLASH_CFI 47#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 48#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 49#define CONFIG_SYS_MAX_FLASH_BANKS 1 50#define CONFIG_SYS_MAX_FLASH_SECT 512 51 52#define CONFIG_ENV_IS_IN_FLASH 1 53#define CONFIG_ENV_OFFSET (128 * 1024) 54#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 55#define CONFIG_ENV_SECT_SIZE (128 * 1024) 56#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 57 58/* Board Clock */ 59#define CONFIG_SYS_CLK_FREQ 36000000 60#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 61#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 62#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 63#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 64 65/* Network interface */ 66#define CONFIG_SMC911X 67#define CONFIG_SMC911X_16_BIT 68#define CONFIG_SMC911X_BASE 0x28000000 69 70#endif /* __RSK7264_H */ 71