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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_XPEDITE550X 1
18#define CONFIG_SYS_BOARD_NAME "XPedite5500"
19#define CONFIG_SYS_FORM_PMC_XMC 1
20#define CONFIG_PRPMC_PCI_ALIAS "pci0"
21#define CONFIG_BOARD_EARLY_INIT_R
22
23#ifndef CONFIG_SYS_TEXT_BASE
24#define CONFIG_SYS_TEXT_BASE 0xfff80000
25#endif
26
27#define CONFIG_PCI_SCAN_SHOW 1
28#define CONFIG_PCIE1 1
29#define CONFIG_FSL_PCI_INIT 1
30#define CONFIG_PCI_INDIRECT_BRIDGE 1
31#define CONFIG_SYS_PCI_64BIT 1
32#define CONFIG_FSL_PCIE_RESET 1
33#define CONFIG_FSL_ELBC 1
34
35
36
37
38#define CONFIG_MP
39#define CONFIG_BPTR_VIRT_ADDR 0xee000000
40#define CONFIG_MPC8xxx_DISABLE_BPTR
41
42
43
44
45#define CONFIG_SPD_EEPROM
46#define CONFIG_DDR_SPD
47#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
48#define SPD_EEPROM_ADDRESS 0x54
49#define SPD_EEPROM_OFFSET 0x200
50#define CONFIG_DIMM_SLOTS_PER_CTLR 1
51#define CONFIG_CHIP_SELECTS_PER_CTRL 2
52#define CONFIG_DDR_ECC
53#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
55#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56#define CONFIG_VERY_BIG_RAM
57
58#ifndef __ASSEMBLY__
59extern unsigned long get_board_sys_clk(unsigned long dummy);
60extern unsigned long get_board_ddr_clk(unsigned long dummy);
61#endif
62
63#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
64#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
65
66
67
68
69#define CONFIG_L2_CACHE
70#define CONFIG_BTB
71#define CONFIG_ENABLE_36BIT_PHYS 1
72
73#define CONFIG_SYS_CCSRBAR 0xef000000
74#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
75
76
77
78
79#define CONFIG_SYS_ALT_MEMTEST
80#define CONFIG_SYS_MEMTEST_START 0x10000000
81#define CONFIG_SYS_MEMTEST_END 0x20000000
82#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
83 CONFIG_SYS_POST_I2C)
84#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
85 CONFIG_SYS_I2C_LM75_ADDR, \
86 CONFIG_SYS_I2C_LM90_ADDR, \
87 CONFIG_SYS_I2C_PCA953X_ADDR0, \
88 CONFIG_SYS_I2C_PCA953X_ADDR2, \
89 CONFIG_SYS_I2C_PCA953X_ADDR3, \
90 CONFIG_SYS_I2C_RTC_ADDR}
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
106
107
108
109
110#define CONFIG_SYS_NAND_BASE 0xef800000
111#define CONFIG_SYS_NAND_BASE2 0xef840000
112#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
113 CONFIG_SYS_NAND_BASE2}
114#define CONFIG_SYS_MAX_NAND_DEVICE 2
115#define CONFIG_NAND_FSL_ELBC
116
117
118
119
120#define CONFIG_SYS_FLASH_BASE 0xf8000000
121#define CONFIG_SYS_FLASH_BASE2 0xf0000000
122#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
123#define CONFIG_SYS_MAX_FLASH_BANKS 2
124#define CONFIG_SYS_MAX_FLASH_SECT 1024
125#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500
127#define CONFIG_FLASH_CFI_DRIVER
128#define CONFIG_SYS_FLASH_CFI
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
130#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
131 {0xf7f40000, 0xc0000} }
132#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
133
134
135
136
137
138#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
139 BR_PS_16 | \
140 BR_V)
141#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
142 OR_GPCM_CSNT | \
143 OR_GPCM_XACS | \
144 OR_GPCM_ACS_DIV2 | \
145 OR_GPCM_SCY_8 | \
146 OR_GPCM_TRLX | \
147 OR_GPCM_EHTR | \
148 OR_GPCM_EAD)
149
150
151#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
152 BR_PS_16 | \
153 BR_V)
154#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
155
156
157#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
158 (2<<BR_DECC_SHIFT) | \
159 BR_PS_8 | \
160 BR_MS_FCM | \
161 BR_V)
162
163
164#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
165 OR_FCM_PGS | \
166 OR_FCM_CSCT | \
167 OR_FCM_CST | \
168 OR_FCM_CHT | \
169 OR_FCM_SCY_1 | \
170 OR_FCM_TRLX | \
171 OR_FCM_EHTR)
172
173
174#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
175 (2<<BR_DECC_SHIFT) | \
176 BR_PS_8 | \
177 BR_MS_FCM | \
178 BR_V)
179#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
180
181
182
183
184#define CONFIG_SYS_INIT_RAM_LOCK 1
185#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
186#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
187
188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
190
191#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
192#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
193
194
195
196
197#define CONFIG_CONS_INDEX 1
198#define CONFIG_SYS_NS16550_SERIAL
199#define CONFIG_SYS_NS16550_REG_SIZE 1
200#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
201#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
202#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
205#define CONFIG_BAUDRATE 115200
206#define CONFIG_LOADS_ECHO 1
207#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
208
209#define CONFIG_FDT_FIXUP_PCI_IRQ 1
210
211
212
213
214#define CONFIG_SYS_I2C
215#define CONFIG_SYS_I2C_FSL
216#define CONFIG_SYS_FSL_I2C_SPEED 400000
217#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219#define CONFIG_SYS_FSL_I2C2_SPEED 400000
220#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
222
223
224#define CONFIG_DTT_LM75
225#define CONFIG_DTT_SENSORS { 0 }
226#define CONFIG_SYS_I2C_LM75_ADDR 0x48
227
228
229#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
230
231
232#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
233#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
234#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
236
237
238#define CONFIG_RTC_M41T11 1
239#define CONFIG_SYS_I2C_RTC_ADDR 0x68
240#define CONFIG_SYS_M41T11_BASE_YEAR 2000
241
242
243#define CONFIG_PCA953X
244#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
245#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
246#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
247#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
248#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
249
250
251
252
253
254#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01
255#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02
256#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04
257#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08
258#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10
259#define CONFIG_SYS_PCA953X_NVM_WP 0x20
260
261
262#define CONFIG_SYS_PCA953X_XMC_GA0 0x01
263#define CONFIG_SYS_PCA953X_XMC_GA1 0x02
264#define CONFIG_SYS_PCA953X_XMC_GA2 0x04
265#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10
266#define CONFIG_SYS_PCA953X_XMC_BIST 0x20
267#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40
268#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80
269
270
271#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01
272#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02
273#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04
274#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08
275#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10
276#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20
277#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40
278#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80
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285
286#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
287#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
288#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000
289#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
290#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
291#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
292
293
294
295
296#define CONFIG_TSEC_ENET
297#define CONFIG_PHY_GIGE 1
298#define CONFIG_TSEC_TBI
299#define CONFIG_MII 1
300#define CONFIG_MII_DEFAULT_TSEC 1
301#define CONFIG_ETHPRIME "eTSEC2"
302
303
304
305
306
307#define CONFIG_TSEC_TBICR_SETTINGS ( \
308 TBICR_PHY_RESET \
309 | TBICR_FULL_DUPLEX \
310 | TBICR_SPEED1_SET \
311 )
312
313#define CONFIG_TSEC1 1
314#define CONFIG_TSEC1_NAME "eTSEC1"
315#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
316#define TSEC1_PHY_ADDR 1
317#define TSEC1_PHYIDX 0
318#define CONFIG_HAS_ETH0
319
320#define CONFIG_TSEC2 1
321#define CONFIG_TSEC2_NAME "eTSEC2"
322#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
323#define TSEC2_PHY_ADDR 2
324#define TSEC2_PHYIDX 0
325#define CONFIG_HAS_ETH1
326
327#define CONFIG_TSEC3 1
328#define CONFIG_TSEC3_NAME "eTSEC3"
329#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
330#define TSEC3_PHY_ADDR 3
331#define TSEC3_PHYIDX 0
332#define CONFIG_HAS_ETH2
333
334
335
336
337#define CONFIG_USB_EHCI
338#define CONFIG_USB_EHCI_FSL
339#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
340#define CONFIG_DOS_PARTITION
341
342
343
344
345#define CONFIG_CMD_DATE
346#define CONFIG_CMD_DTT
347#define CONFIG_CMD_EEPROM
348#define CONFIG_CMD_JFFS2
349#define CONFIG_CMD_NAND
350#define CONFIG_CMD_PCA953X
351#define CONFIG_CMD_PCA953X_INFO
352#define CONFIG_CMD_PCI
353#define CONFIG_CMD_PCI_ENUM
354#define CONFIG_CMD_REGINFO
355
356
357
358
359#define CONFIG_SYS_LONGHELP
360#define CONFIG_SYS_LOAD_ADDR 0x2000000
361#define CONFIG_SYS_CBSIZE 256
362#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
363#define CONFIG_SYS_MAXARGS 16
364#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
365#define CONFIG_CMDLINE_EDITING 1
366#define CONFIG_AUTO_COMPLETE 1
367#define CONFIG_LOADADDR 0x1000000
368#define CONFIG_PANIC_HANG
369#define CONFIG_PREBOOT
370#define CONFIG_INTEGRITY
371
372
373
374
375
376
377#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
378#define CONFIG_SYS_BOOTM_LEN (16 << 20)
379
380
381
382
383#define CONFIG_ENV_IS_IN_FLASH 1
384#define CONFIG_ENV_SECT_SIZE 0x20000
385#define CONFIG_ENV_SIZE 0x8000
386#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
387
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400
401
402#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
403#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
404#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
405#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
406#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
407#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
408
409#define CONFIG_PROG_UBOOT1 \
410 "$download_cmd $loadaddr $ubootfile; " \
411 "if test $? -eq 0; then " \
412 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
413 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
414 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
415 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
416 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
417 "if test $? -ne 0; then " \
418 "echo PROGRAM FAILED; " \
419 "else; " \
420 "echo PROGRAM SUCCEEDED; " \
421 "fi; " \
422 "else; " \
423 "echo DOWNLOAD FAILED; " \
424 "fi;"
425
426#define CONFIG_PROG_UBOOT2 \
427 "$download_cmd $loadaddr $ubootfile; " \
428 "if test $? -eq 0; then " \
429 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
430 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
431 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
432 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
433 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
434 "if test $? -ne 0; then " \
435 "echo PROGRAM FAILED; " \
436 "else; " \
437 "echo PROGRAM SUCCEEDED; " \
438 "fi; " \
439 "else; " \
440 "echo DOWNLOAD FAILED; " \
441 "fi;"
442
443#define CONFIG_BOOT_OS_NET \
444 "$download_cmd $osaddr $osfile; " \
445 "if test $? -eq 0; then " \
446 "if test -n $fdtaddr; then " \
447 "$download_cmd $fdtaddr $fdtfile; " \
448 "if test $? -eq 0; then " \
449 "bootm $osaddr - $fdtaddr; " \
450 "else; " \
451 "echo FDT DOWNLOAD FAILED; " \
452 "fi; " \
453 "else; " \
454 "bootm $osaddr; " \
455 "fi; " \
456 "else; " \
457 "echo OS DOWNLOAD FAILED; " \
458 "fi;"
459
460#define CONFIG_PROG_OS1 \
461 "$download_cmd $osaddr $osfile; " \
462 "if test $? -eq 0; then " \
463 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
464 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
465 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
466 "if test $? -ne 0; then " \
467 "echo OS PROGRAM FAILED; " \
468 "else; " \
469 "echo OS PROGRAM SUCCEEDED; " \
470 "fi; " \
471 "else; " \
472 "echo OS DOWNLOAD FAILED; " \
473 "fi;"
474
475#define CONFIG_PROG_OS2 \
476 "$download_cmd $osaddr $osfile; " \
477 "if test $? -eq 0; then " \
478 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
479 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
480 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
481 "if test $? -ne 0; then " \
482 "echo OS PROGRAM FAILED; " \
483 "else; " \
484 "echo OS PROGRAM SUCCEEDED; " \
485 "fi; " \
486 "else; " \
487 "echo OS DOWNLOAD FAILED; " \
488 "fi;"
489
490#define CONFIG_PROG_FDT1 \
491 "$download_cmd $fdtaddr $fdtfile; " \
492 "if test $? -eq 0; then " \
493 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
494 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
495 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
496 "if test $? -ne 0; then " \
497 "echo FDT PROGRAM FAILED; " \
498 "else; " \
499 "echo FDT PROGRAM SUCCEEDED; " \
500 "fi; " \
501 "else; " \
502 "echo FDT DOWNLOAD FAILED; " \
503 "fi;"
504
505#define CONFIG_PROG_FDT2 \
506 "$download_cmd $fdtaddr $fdtfile; " \
507 "if test $? -eq 0; then " \
508 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
509 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
510 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
511 "if test $? -ne 0; then " \
512 "echo FDT PROGRAM FAILED; " \
513 "else; " \
514 "echo FDT PROGRAM SUCCEEDED; " \
515 "fi; " \
516 "else; " \
517 "echo FDT DOWNLOAD FAILED; " \
518 "fi;"
519
520#define CONFIG_EXTRA_ENV_SETTINGS \
521 "autoload=yes\0" \
522 "download_cmd=tftp\0" \
523 "console_args=console=ttyS0,115200\0" \
524 "root_args=root=/dev/nfs rw\0" \
525 "misc_args=ip=on\0" \
526 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
527 "bootfile=/home/user/file\0" \
528 "osfile=/home/user/board.uImage\0" \
529 "fdtfile=/home/user/board.dtb\0" \
530 "ubootfile=/home/user/u-boot.bin\0" \
531 "fdtaddr=0x1e00000\0" \
532 "osaddr=0x1000000\0" \
533 "loadaddr=0x1000000\0" \
534 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
535 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
536 "prog_os1="CONFIG_PROG_OS1"\0" \
537 "prog_os2="CONFIG_PROG_OS2"\0" \
538 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
539 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
540 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
541 "bootcmd_flash1=run set_bootargs; " \
542 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
543 "bootcmd_flash2=run set_bootargs; " \
544 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
545 "bootcmd=run bootcmd_flash1\0"
546#endif
547