1/* 2 * (C) Copyright 2005-2007 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/************************************************************************ 9 * yosemite.h - configuration for Yosemite & Yellowstone boards 10 ***********************************************************************/ 11#ifndef __CONFIG_H 12#define __CONFIG_H 13 14/*----------------------------------------------------------------------- 15 * High Level Configuration Options 16 *----------------------------------------------------------------------*/ 17/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ 18#ifndef CONFIG_YELLOWSTONE 19#define CONFIG_440EP 1 /* Specific PPC440EP support */ 20#define CONFIG_HOSTNAME yosemite 21#else 22#define CONFIG_440GR 1 /* Specific PPC440GR support */ 23#define CONFIG_HOSTNAME yellowstone 24#endif 25#define CONFIG_440 1 /* ... PPC440 family */ 26#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ 27 28#define CONFIG_SYS_TEXT_BASE 0xFFF80000 29 30/* 31 * Include common defines/options for all AMCC eval boards 32 */ 33#include "amcc-common.h" 34 35#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 36#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 37#define CONFIG_BOARD_RESET 1 /* call board_reset() */ 38 39/*----------------------------------------------------------------------- 40 * Base addresses -- Note these are effective addresses where the 41 * actual resources get mapped (not physical addresses) 42 *----------------------------------------------------------------------*/ 43#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ 44#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ 45#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 46#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 47#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 48 49/*Don't change either of these*/ 50#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ 51/*Don't change either of these*/ 52 53#define CONFIG_SYS_USB_DEVICE 0x50000000 54#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 55#define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000) 56#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 57 58/*----------------------------------------------------------------------- 59 * Initial RAM & stack pointer (placed in SDRAM) 60 *----------------------------------------------------------------------*/ 61#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ 62#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ 63#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) 64#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 65#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 66 67/*----------------------------------------------------------------------- 68 * Serial Port 69 *----------------------------------------------------------------------*/ 70#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 71#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ 72 73/*----------------------------------------------------------------------- 74 * Environment 75 *----------------------------------------------------------------------*/ 76/* 77 * Define here the location of the environment variables (FLASH or EEPROM). 78 * Note: DENX encourages to use redundant environment in FLASH. 79 */ 80#if 1 81#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 82#else 83#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 84#endif 85 86/*----------------------------------------------------------------------- 87 * FLASH related 88 *----------------------------------------------------------------------*/ 89#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 90#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 91#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ 92 93#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 94#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 95 96#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 97#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 98 99#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 100 101#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 102 103#ifdef CONFIG_ENV_IS_IN_FLASH 104#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 105#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 106#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 107 108/* Address and size of Redundant Environment Sector */ 109#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 110#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 111#endif /* CONFIG_ENV_IS_IN_FLASH */ 112 113/*----------------------------------------------------------------------- 114 * DDR SDRAM 115 *----------------------------------------------------------------------*/ 116#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ 117#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ 118#define CONFIG_SYS_SDRAM_BANKS (2) 119 120/*----------------------------------------------------------------------- 121 * I2C 122 *----------------------------------------------------------------------*/ 123#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 124 125#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) 126#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 127#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 128#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 129 130#ifdef CONFIG_ENV_IS_IN_EEPROM 131#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ 132#define CONFIG_ENV_OFFSET 0x0 133#endif /* CONFIG_ENV_IS_IN_EEPROM */ 134 135/* I2C SYSMON (LM75, AD7414 is almost compatible) */ 136#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 137#define CONFIG_DTT_AD7414 1 /* use AD7414 */ 138#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 139#define CONFIG_SYS_DTT_MAX_TEMP 70 140#define CONFIG_SYS_DTT_LOW_TEMP -30 141#define CONFIG_SYS_DTT_HYSTERESIS 3 142 143/* 144 * Default environment variables 145 */ 146#define CONFIG_EXTRA_ENV_SETTINGS \ 147 CONFIG_AMCC_DEF_ENV \ 148 CONFIG_AMCC_DEF_ENV_POWERPC \ 149 CONFIG_AMCC_DEF_ENV_PPC_OLD \ 150 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 151 "kernel_addr=fc000000\0" \ 152 "ramdisk_addr=fc180000\0" \ 153 "" 154 155#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ 156#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ 157#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ 158#define CONFIG_PHY1_ADDR 3 159 160/* Partitions */ 161#define CONFIG_MAC_PARTITION 162#define CONFIG_DOS_PARTITION 163#define CONFIG_ISO_PARTITION 164 165#ifdef CONFIG_440EP 166/* USB */ 167#define CONFIG_USB_OHCI_NEW 168#define CONFIG_SYS_OHCI_BE_CONTROLLER 169 170#undef CONFIG_SYS_USB_OHCI_BOARD_INIT 171#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 172#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000) 173#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" 174#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 175 176/* Comment this out to enable USB 1.1 device */ 177#define USB_2_0_DEVICE 178 179#define CONFIG_SUPPORT_VFAT 180#endif /* CONFIG_440EP */ 181 182#ifdef DEBUG 183#define CONFIG_PANIC_HANG 184#else 185#define CONFIG_HW_WATCHDOG /* watchdog */ 186#endif 187 188/* 189 * Commands additional to the ones defined in amcc-common.h 190 */ 191#define CONFIG_CMD_DTT 192#define CONFIG_CMD_PCI 193 194#ifdef CONFIG_440EP 195#endif 196 197/*----------------------------------------------------------------------- 198 * PCI stuff 199 *----------------------------------------------------------------------- 200 */ 201/* General PCI */ 202#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 203#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 204#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ 205 206/* Board-specific PCI */ 207#define CONFIG_SYS_PCI_TARGET_INIT 208#define CONFIG_SYS_PCI_MASTER_INIT 209 210#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 211#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ 212 213/*----------------------------------------------------------------------- 214 * External Bus Controller (EBC) Setup 215 *----------------------------------------------------------------------*/ 216#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE 217#define CONFIG_SYS_CPLD 0x80000000 218 219/* Memory Bank 0 (NOR-FLASH) initialization */ 220#define CONFIG_SYS_EBC_PB0AP 0x03017300 221#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) 222 223/* Memory Bank 2 (CPLD) initialization */ 224#define CONFIG_SYS_EBC_PB2AP 0x04814500 225#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000) 226 227#define CONFIG_SYS_BCSR5_PCI66EN 0x80 228 229#endif /* __CONFIG_H */ 230