1
2
3
4
5
6#ifndef _FSL_DPNI_H
7#define _FSL_DPNI_H
8
9
10#define DPNI_VER_MAJOR 6
11#define DPNI_VER_MINOR 0
12
13
14#define DPNI_CMDID_OPEN 0x801
15#define DPNI_CMDID_CLOSE 0x800
16#define DPNI_CMDID_CREATE 0x901
17#define DPNI_CMDID_DESTROY 0x900
18
19#define DPNI_CMDID_ENABLE 0x002
20#define DPNI_CMDID_DISABLE 0x003
21#define DPNI_CMDID_GET_ATTR 0x004
22#define DPNI_CMDID_RESET 0x005
23
24#define DPNI_CMDID_SET_POOLS 0x200
25#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201
26#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202
27#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203
28#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204
29#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205
30#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206
31#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B
32
33#define DPNI_CMDID_GET_QDID 0x210
34#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212
35#define DPNI_CMDID_GET_COUNTER 0x213
36#define DPNI_CMDID_SET_COUNTER 0x214
37#define DPNI_CMDID_GET_LINK_STATE 0x215
38#define DPNI_CMDID_SET_LINK_CFG 0x21A
39
40#define DPNI_CMDID_SET_PRIM_MAC 0x224
41#define DPNI_CMDID_GET_PRIM_MAC 0x225
42#define DPNI_CMDID_ADD_MAC_ADDR 0x226
43#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227
44
45#define DPNI_CMDID_SET_TX_FLOW 0x236
46#define DPNI_CMDID_GET_TX_FLOW 0x237
47#define DPNI_CMDID_SET_RX_FLOW 0x238
48#define DPNI_CMDID_GET_RX_FLOW 0x239
49#define DPNI_CMDID_SET_TX_CONF 0x257
50#define DPNI_CMDID_GET_TX_CONF 0x258
51
52
53#define DPNI_CMD_OPEN(cmd, dpni_id) \
54 MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
55
56#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \
57do { \
58 MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
59 MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
60 MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
61 MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
62 MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
63 MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
64 MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
65 MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
66 MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
67 MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
68 MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
69 MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
70 MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
71 MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
72 MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
73 MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
74 MC_PREP_OP(ext, 4, 0, 16, uint16_t, \
75 cfg->ipr_cfg.max_open_frames_ipv4); \
76 MC_PREP_OP(ext, 4, 16, 16, uint16_t, \
77 cfg->ipr_cfg.max_open_frames_ipv6); \
78 MC_PREP_OP(ext, 4, 32, 16, uint16_t, \
79 cfg->ipr_cfg.max_reass_frm_size); \
80 MC_PREP_OP(ext, 5, 0, 16, uint16_t, \
81 cfg->ipr_cfg.min_frag_size_ipv4); \
82 MC_PREP_OP(ext, 5, 16, 16, uint16_t, \
83 cfg->ipr_cfg.min_frag_size_ipv6); \
84} while (0)
85
86#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \
87do { \
88 MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
89 MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
90 MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
91 MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
92 MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
93 MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
94 MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
95 MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
96 MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
97 MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
98 MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
99 MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
100 MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
101 MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
102 MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
103 MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
104 MC_EXT_OP(ext, 4, 0, 16, uint16_t, \
105 cfg->ipr_cfg.max_open_frames_ipv4); \
106 MC_EXT_OP(ext, 4, 16, 16, uint16_t, \
107 cfg->ipr_cfg.max_open_frames_ipv6); \
108 MC_EXT_OP(ext, 4, 32, 16, uint16_t, \
109 cfg->ipr_cfg.max_reass_frm_size); \
110 MC_EXT_OP(ext, 5, 0, 16, uint16_t, \
111 cfg->ipr_cfg.min_frag_size_ipv4); \
112 MC_EXT_OP(ext, 5, 16, 16, uint16_t, \
113 cfg->ipr_cfg.min_frag_size_ipv6); \
114} while (0)
115
116
117#define DPNI_CMD_CREATE(cmd, cfg) \
118do { \
119 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \
120 MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \
121 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \
122 MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \
123 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \
124 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \
125 MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \
126 MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \
127 MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \
128 MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \
129 MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \
130 MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \
131 MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \
132 MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
133 MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
134 MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
135 MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
136 MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
137 MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \
138} while (0)
139
140
141#define DPNI_CMD_SET_POOLS(cmd, cfg) \
142do { \
143 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \
144 MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \
145 MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \
146 MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \
147 MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \
148 MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \
149 MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \
150 MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \
151 MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \
152 MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \
153 MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
154 MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \
155 MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
156 MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \
157 MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\
158 MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \
159 MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
160 MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \
161 MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
162 MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \
163 MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
164 MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \
165 MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\
166 MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \
167 MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
168} while (0)
169
170
171#define DPNI_CMD_GET_ATTR(cmd, attr) \
172 MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova)
173
174
175#define DPNI_RSP_GET_ATTR(cmd, attr) \
176do { \
177 MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
178 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \
179 MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \
180 MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \
181 MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options); \
182 MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \
183 MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\
184 MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \
185 MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \
186 MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \
187 MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \
188 MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \
189 MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \
190 MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\
191 MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\
192} while (0)
193
194
195#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
196do { \
197 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \
198 MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \
199 MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \
200} while (0)
201
202
203#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \
204do { \
205 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
206 MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
207 MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
208 MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
209 MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
210 MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
211 MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
212} while (0)
213
214
215#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \
216do { \
217 MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
218 MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
219 MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
220 MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
221 MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
222 MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
223 MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
224 MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
225} while (0)
226
227
228#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \
229do { \
230 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
231 MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
232 MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
233 MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
234 MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
235 MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
236 MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
237} while (0)
238
239
240#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \
241do { \
242 MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
243 MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
244 MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
245 MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
246 MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
247 MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
248 MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
249 MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
250} while (0)
251
252
253#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
254do { \
255 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
256 MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
257 MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
258 MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
259 MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
260 MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
261 MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
262} while (0)
263
264
265#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
266do { \
267 MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
268 MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
269 MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
270 MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
271 MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
272 MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
273 MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
274 MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
275} while (0)
276
277
278#define DPNI_RSP_GET_QDID(cmd, qdid) \
279 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid)
280
281
282#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \
283 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset)
284
285
286#define DPNI_CMD_GET_COUNTER(cmd, counter) \
287 MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter)
288
289
290#define DPNI_RSP_GET_COUNTER(cmd, value) \
291 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value)
292
293
294#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \
295do { \
296 MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \
297 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \
298} while (0)
299
300
301#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \
302do { \
303 MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\
304 MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\
305} while (0)
306
307
308#define DPNI_RSP_GET_LINK_STATE(cmd, state) \
309do { \
310 MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\
311 MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\
312 MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\
313} while (0)
314
315
316
317
318#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
319do { \
320 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
321 MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
322 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
323 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
324 MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
325 MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
326} while (0)
327
328
329#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
330do { \
331 MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
332 MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
333 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
334 MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
335 MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
336 MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
337} while (0)
338
339
340#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \
341do { \
342 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
343 MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
344 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
345 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
346 MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
347 MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
348} while (0)
349
350
351#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \
352do { \
353 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
354 MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
355 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
356 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
357 MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
358 MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
359} while (0)
360
361
362#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \
363do { \
364 MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\
365 MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\
366 MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\
367 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\
368 MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
369} while (0)
370
371
372#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \
373 MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id)
374
375
376#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \
377 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
378
379
380#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \
381do { \
382 MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\
383 MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\
384 MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\
385} while (0)
386
387
388#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \
389do { \
390 MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
391 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
392 MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\
393 MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\
394 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
395 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
396 MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \
397 MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \
398 MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \
399 MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
400 cfg->flc_cfg.frame_data_size);\
401 MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
402 cfg->flc_cfg.flow_context_size);\
403 MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\
404 MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\
405 MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \
406} while (0)
407
408
409#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \
410do { \
411 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
412 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
413} while (0)
414
415
416#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \
417do { \
418 MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \
419 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
420 MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \
421 MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
422 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \
423 MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \
424 MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \
425 MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \
426 MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
427 attr->flc_cfg.frame_data_size);\
428 MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
429 attr->flc_cfg.flow_context_size);\
430 MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\
431 MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\
432} while (0)
433
434#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \
435do { \
436 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \
437 MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \
438 cfg->queue_cfg.dest_cfg.dest_type); \
439 MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \
440 MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \
441 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
442 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \
443 MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \
444 MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \
445 MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \
446 cfg->queue_cfg.tail_drop_threshold); \
447 MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
448 cfg->queue_cfg.flc_cfg.flc_type); \
449 MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
450 cfg->queue_cfg.flc_cfg.frame_data_size); \
451 MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
452 cfg->queue_cfg.flc_cfg.flow_context_size); \
453 MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \
454 MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \
455 cfg->queue_cfg.flc_cfg.flow_context); \
456} while (0)
457
458#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \
459 MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
460
461#define DPNI_RSP_GET_TX_CONF(cmd, attr) \
462do { \
463 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \
464 attr->queue_attr.dest_cfg.priority); \
465 MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \
466 attr->queue_attr.dest_cfg.dest_type); \
467 MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \
468 MC_RSP_OP(cmd, 0, 46, 1, int, \
469 attr->queue_attr.order_preservation_en); \
470 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \
471 MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \
472 MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \
473 attr->queue_attr.tail_drop_threshold); \
474 MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \
475 MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
476 attr->queue_attr.flc_cfg.flc_type); \
477 MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
478 attr->queue_attr.flc_cfg.frame_data_size); \
479 MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
480 attr->queue_attr.flc_cfg.flow_context_size); \
481 MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \
482 MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \
483 attr->queue_attr.flc_cfg.flow_context); \
484} while (0)
485
486enum net_prot {
487 NET_PROT_NONE = 0,
488 NET_PROT_PAYLOAD,
489 NET_PROT_ETH,
490 NET_PROT_VLAN,
491 NET_PROT_IPV4,
492 NET_PROT_IPV6,
493 NET_PROT_IP,
494 NET_PROT_TCP,
495 NET_PROT_UDP,
496 NET_PROT_UDP_LITE,
497 NET_PROT_IPHC,
498 NET_PROT_SCTP,
499 NET_PROT_SCTP_CHUNK_DATA,
500 NET_PROT_PPPOE,
501 NET_PROT_PPP,
502 NET_PROT_PPPMUX,
503 NET_PROT_PPPMUX_SUBFRM,
504 NET_PROT_L2TPV2,
505 NET_PROT_L2TPV3_CTRL,
506 NET_PROT_L2TPV3_SESS,
507 NET_PROT_LLC,
508 NET_PROT_LLC_SNAP,
509 NET_PROT_NLPID,
510 NET_PROT_SNAP,
511 NET_PROT_MPLS,
512 NET_PROT_IPSEC_AH,
513 NET_PROT_IPSEC_ESP,
514 NET_PROT_UDP_ENC_ESP,
515 NET_PROT_MACSEC,
516 NET_PROT_GRE,
517 NET_PROT_MINENCAP,
518 NET_PROT_DCCP,
519 NET_PROT_ICMP,
520 NET_PROT_IGMP,
521 NET_PROT_ARP,
522 NET_PROT_CAPWAP_DATA,
523 NET_PROT_CAPWAP_CTRL,
524 NET_PROT_RFC2684,
525 NET_PROT_ICMPV6,
526 NET_PROT_FCOE,
527 NET_PROT_FIP,
528 NET_PROT_ISCSI,
529 NET_PROT_GTP,
530 NET_PROT_USER_DEFINED_L2,
531 NET_PROT_USER_DEFINED_L3,
532 NET_PROT_USER_DEFINED_L4,
533 NET_PROT_USER_DEFINED_L5,
534 NET_PROT_USER_DEFINED_SHIM1,
535 NET_PROT_USER_DEFINED_SHIM2,
536
537 NET_PROT_DUMMY_LAST
538};
539
540
541
542
543
544
545struct fsl_mc_io;
546
547
548
549
550#define DPNI_MAX_TC 8
551
552#define DPNI_MAX_DPBP 8
553
554
555#define DPNI_ALL_TCS (uint8_t)(-1)
556
557#define DPNI_ALL_TC_FLOWS (uint16_t)(-1)
558
559#define DPNI_NEW_FLOW_ID (uint16_t)(-1)
560
561#define DPNI_COMMON_TX_CONF (uint16_t)(-1)
562
563
564
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566
567
568
569
570
571
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577
578
579
580int dpni_open(struct fsl_mc_io *mc_io,
581 uint32_t cmd_flags,
582 int dpni_id,
583 uint16_t *token);
584
585
586
587
588
589
590
591
592
593
594
595
596int dpni_close(struct fsl_mc_io *mc_io,
597 uint32_t cmd_flags,
598 uint16_t token);
599
600
601
602
603
604
605
606#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001
607
608
609
610
611
612#define DPNI_OPT_TX_CONF_DISABLED 0x00000002
613
614
615#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004
616
617
618
619
620
621#define DPNI_OPT_DIST_HASH 0x00000010
622
623
624
625
626
627
628#define DPNI_OPT_DIST_FS 0x00000020
629
630
631#define DPNI_OPT_UNICAST_FILTER 0x00000080
632
633#define DPNI_OPT_MULTICAST_FILTER 0x00000100
634
635#define DPNI_OPT_VLAN_FILTER 0x00000200
636
637#define DPNI_OPT_IPR 0x00000800
638
639#define DPNI_OPT_IPF 0x00001000
640
641#define DPNI_OPT_VLAN_MANIPULATION 0x00010000
642
643#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000
644
645#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
646
647
648
649
650
651
652struct dpni_extended_cfg {
653
654
655
656
657
658
659
660
661
662
663
664 struct {
665 uint16_t max_dist;
666 uint16_t max_fs_entries;
667 } tc_cfg[DPNI_MAX_TC];
668
669
670
671
672
673
674
675
676
677
678 struct {
679 uint16_t max_reass_frm_size;
680 uint16_t min_frag_size_ipv4;
681 uint16_t min_frag_size_ipv6;
682 uint16_t max_open_frames_ipv4;
683 uint16_t max_open_frames_ipv6;
684 } ipr_cfg;
685};
686
687
688
689
690
691
692
693
694int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
695 uint8_t *ext_cfg_buf);
696
697
698
699
700
701
702
703struct dpni_cfg {
704 uint8_t mac_addr[6];
705
706
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710
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715
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719
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735
736
737 struct {
738 uint32_t options;
739 enum net_prot start_hdr;
740 uint8_t max_senders;
741 uint8_t max_tcs;
742 uint8_t max_unicast_filters;
743 uint8_t max_multicast_filters;
744 uint8_t max_vlan_filters;
745 uint8_t max_qos_entries;
746 uint8_t max_qos_key_size;
747 uint8_t max_dist_key_size;
748 uint8_t max_policers;
749 uint8_t max_congestion_ctrl;
750 uint64_t ext_cfg_iova;
751 } adv;
752};
753
754
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775
776int dpni_create(struct fsl_mc_io *mc_io,
777 uint32_t cmd_flags,
778 const struct dpni_cfg *cfg,
779 uint16_t *token);
780
781
782
783
784
785
786
787
788
789int dpni_destroy(struct fsl_mc_io *mc_io,
790 uint32_t cmd_flags,
791 uint16_t token);
792
793
794
795
796
797
798
799struct dpni_pools_cfg {
800 uint8_t num_dpbp;
801
802
803
804
805
806
807 struct {
808 int dpbp_id;
809 uint16_t buffer_size;
810 int backup_pool;
811 } pools[DPNI_MAX_DPBP];
812};
813
814
815
816
817
818
819
820
821
822
823
824
825
826int dpni_set_pools(struct fsl_mc_io *mc_io,
827 uint32_t cmd_flags,
828 uint16_t token,
829 const struct dpni_pools_cfg *cfg);
830
831
832
833
834
835
836
837
838
839int dpni_enable(struct fsl_mc_io *mc_io,
840 uint32_t cmd_flags,
841 uint16_t token);
842
843
844
845
846
847
848
849
850
851int dpni_disable(struct fsl_mc_io *mc_io,
852 uint32_t cmd_flags,
853 uint16_t token);
854
855
856
857
858
859
860
861
862
863
864int dpni_reset(struct fsl_mc_io *mc_io,
865 uint32_t cmd_flags,
866 uint16_t token);
867
868
869
870
871
872
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875
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887
888
889struct dpni_attr {
890 int id;
891
892
893
894
895
896 struct {
897 uint16_t major;
898 uint16_t minor;
899 } version;
900 enum net_prot start_hdr;
901 uint32_t options;
902 uint8_t max_senders;
903 uint8_t max_tcs;
904 uint8_t max_unicast_filters;
905 uint8_t max_multicast_filters;
906 uint8_t max_vlan_filters;
907 uint8_t max_qos_entries;
908 uint8_t max_qos_key_size;
909 uint8_t max_dist_key_size;
910 uint8_t max_policers;
911 uint8_t max_congestion_ctrl;
912 uint64_t ext_cfg_iova;
913};
914
915
916
917
918
919
920
921
922
923
924int dpni_get_attributes(struct fsl_mc_io *mc_io,
925 uint32_t cmd_flags,
926 uint16_t token,
927 struct dpni_attr *attr);
928
929
930
931
932
933
934
935
936int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
937 const uint8_t *ext_cfg_buf);
938
939
940
941
942
943
944
945
946#define DPNI_ERROR_EOFHE 0x00020000
947
948
949
950#define DPNI_ERROR_FLE 0x00002000
951
952
953
954#define DPNI_ERROR_FPE 0x00001000
955
956
957
958#define DPNI_ERROR_PHE 0x00000020
959
960
961
962#define DPNI_ERROR_L3CE 0x00000004
963
964
965
966#define DPNI_ERROR_L4CE 0x00000001
967
968
969
970
971
972
973
974enum dpni_error_action {
975 DPNI_ERROR_ACTION_DISCARD = 0,
976 DPNI_ERROR_ACTION_CONTINUE = 1,
977 DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
978};
979
980
981
982
983
984
985
986
987struct dpni_error_cfg {
988 uint32_t errors;
989 enum dpni_error_action error_action;
990 int set_frame_annotation;
991};
992
993
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1003
1004
1005int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
1006 uint32_t cmd_flags,
1007 uint16_t token,
1008 struct dpni_error_cfg *cfg);
1009
1010
1011
1012
1013#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001
1014
1015#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002
1016
1017#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004
1018
1019#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008
1020
1021#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010
1022
1023#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020
1024
1025#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040
1026
1027
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1030
1031
1032
1033
1034
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1037
1038
1039struct dpni_buffer_layout {
1040 uint32_t options;
1041 int pass_timestamp;
1042 int pass_parser_result;
1043 int pass_frame_status;
1044 uint16_t private_data_size;
1045 uint16_t data_align;
1046 uint16_t data_head_room;
1047 uint16_t data_tail_room;
1048};
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
1060 uint32_t cmd_flags,
1061 uint16_t token,
1062 struct dpni_buffer_layout *layout);
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io,
1076 uint32_t cmd_flags,
1077 uint16_t token,
1078 const struct dpni_buffer_layout *layout);
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io,
1090 uint32_t cmd_flags,
1091 uint16_t token,
1092 struct dpni_buffer_layout *layout);
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io,
1106 uint32_t cmd_flags,
1107 uint16_t token,
1108 const struct dpni_buffer_layout *layout);
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
1121 uint32_t cmd_flags,
1122 uint16_t token,
1123 struct dpni_buffer_layout *layout);
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
1138 uint32_t cmd_flags,
1139 uint16_t token,
1140 const struct dpni_buffer_layout *layout);
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153int dpni_get_qdid(struct fsl_mc_io *mc_io,
1154 uint32_t cmd_flags,
1155 uint16_t token,
1156 uint16_t *qdid);
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
1168 uint32_t cmd_flags,
1169 uint16_t token,
1170 uint16_t *data_offset);
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187enum dpni_counter {
1188 DPNI_CNT_ING_FRAME = 0x0,
1189 DPNI_CNT_ING_BYTE = 0x1,
1190 DPNI_CNT_ING_FRAME_DROP = 0x2,
1191 DPNI_CNT_ING_FRAME_DISCARD = 0x3,
1192 DPNI_CNT_ING_MCAST_FRAME = 0x4,
1193 DPNI_CNT_ING_MCAST_BYTE = 0x5,
1194 DPNI_CNT_ING_BCAST_FRAME = 0x6,
1195 DPNI_CNT_ING_BCAST_BYTES = 0x7,
1196 DPNI_CNT_EGR_FRAME = 0x8,
1197 DPNI_CNT_EGR_BYTE = 0x9,
1198 DPNI_CNT_EGR_FRAME_DISCARD = 0xa
1199};
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211int dpni_get_counter(struct fsl_mc_io *mc_io,
1212 uint32_t cmd_flags,
1213 uint16_t token,
1214 enum dpni_counter counter,
1215 uint64_t *value);
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228int dpni_set_counter(struct fsl_mc_io *mc_io,
1229 uint32_t cmd_flags,
1230 uint16_t token,
1231 enum dpni_counter counter,
1232 uint64_t value);
1233
1234
1235#define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL
1236
1237#define DPNI_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
1238
1239#define DPNI_LINK_OPT_PAUSE 0x0000000000000004ULL
1240
1241#define DPNI_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
1242
1243
1244
1245
1246
1247
1248struct dpni_link_cfg {
1249 uint32_t rate;
1250 uint64_t options;
1251};
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
1263 uint32_t cmd_flags,
1264 uint16_t token,
1265 const struct dpni_link_cfg *cfg);
1266
1267
1268
1269
1270
1271
1272
1273struct dpni_link_state {
1274 uint32_t rate;
1275 uint64_t options;
1276 int up;
1277};
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288int dpni_get_link_state(struct fsl_mc_io *mc_io,
1289 uint32_t cmd_flags,
1290 uint16_t token,
1291 struct dpni_link_state *state);
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
1303 uint32_t cmd_flags,
1304 uint16_t token,
1305 const uint8_t mac_addr[6]);
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
1317 uint32_t cmd_flags,
1318 uint16_t token,
1319 uint8_t mac_addr[6]);
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
1331 uint32_t cmd_flags,
1332 uint16_t token,
1333 const uint8_t mac_addr[6]);
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1344int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
1345 uint32_t cmd_flags,
1346 uint16_t token,
1347 const uint8_t mac_addr[6]);
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1362enum dpni_dest {
1363 DPNI_DEST_NONE = 0,
1364 DPNI_DEST_DPIO = 1,
1365 DPNI_DEST_DPCON = 2
1366};
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1376struct dpni_dest_cfg {
1377 enum dpni_dest dest_type;
1378 int dest_id;
1379 uint8_t priority;
1380};
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1387enum dpni_flc_type {
1388 DPNI_FLC_USER_DEFINED = 0,
1389 DPNI_FLC_STASH = 1,
1390};
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1399enum dpni_stash_size {
1400 DPNI_STASH_SIZE_0B = 0,
1401 DPNI_STASH_SIZE_64B = 1,
1402 DPNI_STASH_SIZE_128B = 2,
1403 DPNI_STASH_SIZE_192B = 3,
1404};
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1409#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001
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1426struct dpni_flc_cfg {
1427 enum dpni_flc_type flc_type;
1428 uint32_t options;
1429 enum dpni_stash_size frame_data_size;
1430 enum dpni_stash_size flow_context_size;
1431 uint64_t flow_context;
1432};
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1437#define DPNI_QUEUE_OPT_USER_CTX 0x00000001
1438
1439#define DPNI_QUEUE_OPT_DEST 0x00000002
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1443#define DPNI_QUEUE_OPT_FLC 0x00000004
1444
1445#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008
1446
1447#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010
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1471struct dpni_queue_cfg {
1472 uint32_t options;
1473 uint64_t user_ctx;
1474 struct dpni_dest_cfg dest_cfg;
1475 struct dpni_flc_cfg flc_cfg;
1476 int order_preservation_en;
1477 uint32_t tail_drop_threshold;
1478};
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1490struct dpni_queue_attr {
1491 uint64_t user_ctx;
1492 struct dpni_dest_cfg dest_cfg;
1493 struct dpni_flc_cfg flc_cfg;
1494 int order_preservation_en;
1495 uint32_t tail_drop_threshold;
1496 uint32_t fqid;
1497};
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1501
1502#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001
1503
1504#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010
1505
1506#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020
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1522struct dpni_tx_flow_cfg {
1523 uint32_t options;
1524 int use_common_tx_conf_queue;
1525 int l3_chksum_gen;
1526 int l4_chksum_gen;
1527};
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1542int dpni_set_tx_flow(struct fsl_mc_io *mc_io,
1543 uint32_t cmd_flags,
1544 uint16_t token,
1545 uint16_t *flow_id,
1546 const struct dpni_tx_flow_cfg *cfg);
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1555struct dpni_tx_flow_attr {
1556 int use_common_tx_conf_queue;
1557 int l3_chksum_gen;
1558 int l4_chksum_gen;
1559};
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1572int dpni_get_tx_flow(struct fsl_mc_io *mc_io,
1573 uint32_t cmd_flags,
1574 uint16_t token,
1575 uint16_t flow_id,
1576 struct dpni_tx_flow_attr *attr);
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1584struct dpni_tx_conf_cfg {
1585 int errors_only;
1586 struct dpni_queue_cfg queue_cfg;
1587};
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1609int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
1610 uint32_t cmd_flags,
1611 uint16_t token,
1612 uint16_t flow_id,
1613 const struct dpni_tx_conf_cfg *cfg);
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1621struct dpni_tx_conf_attr {
1622 int errors_only;
1623 struct dpni_queue_attr queue_attr;
1624};
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1643int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
1644 uint32_t cmd_flags,
1645 uint16_t token,
1646 uint16_t flow_id,
1647 struct dpni_tx_conf_attr *attr);
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1663int dpni_set_rx_flow(struct fsl_mc_io *mc_io,
1664 uint32_t cmd_flags,
1665 uint16_t token,
1666 uint8_t tc_id,
1667 uint16_t flow_id,
1668 const struct dpni_queue_cfg *cfg);
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1681int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
1682 uint32_t cmd_flags,
1683 uint16_t token,
1684 uint8_t tc_id,
1685 uint16_t flow_id,
1686 struct dpni_queue_attr *attr);
1687
1688#endif
1689