LXR uboot/post/cpu/mpc8xx/cache.c

   1/*
   2 * (C) Copyright 2002
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9
  10/* Cache test
  11 *
  12 * This test verifies the CPU data and instruction cache using
  13 * several test scenarios.
  14 */
  15
  16#include <post.h>
  17#include <watchdog.h>
  18
  19#if CONFIG_POST & CONFIG_SYS_POST_CACHE
  20
  21#define CACHE_POST_SIZE 1024
  22
  23extern int cache_post_test1 (char *, unsigned int);
  24extern int cache_post_test2 (char *, unsigned int);
  25extern int cache_post_test3 (char *, unsigned int);
  26extern int cache_post_test4 (char *, unsigned int);
  27extern int cache_post_test5 (void);
  28extern int cache_post_test6 (void);
  29
  30int cache_post_test (int flags)
  31{
  32        int ints = disable_interrupts ();
  33        int res = 0;
  34        static char ta[CACHE_POST_SIZE + 0xf];
  35        char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf);
  36
  37        WATCHDOG_RESET ();
  38        if (res == 0)
  39                res = cache_post_test1 (testarea, CACHE_POST_SIZE);
  40        WATCHDOG_RESET ();
  41        if (res == 0)
  42                res = cache_post_test2 (testarea, CACHE_POST_SIZE);
  43        WATCHDOG_RESET ();
  44        if (res == 0)
  45                res = cache_post_test3 (testarea, CACHE_POST_SIZE);
  46        WATCHDOG_RESET ();
  47        if (res == 0)
  48                res = cache_post_test4 (testarea, CACHE_POST_SIZE);
  49        WATCHDOG_RESET ();
  50        if (res == 0)
  51                res = cache_post_test5 ();
  52        WATCHDOG_RESET ();
  53        if (res == 0)
  54                res = cache_post_test6 ();
  55
  56        WATCHDOG_RESET ();
  57        if (ints)
  58                enable_interrupts ();
  59        return res;
  60}
  61
  62#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
  63