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9#ifndef _MEM_H_
10#define _MEM_H_
11
12#define CS0 0x0
13#define CS1 0x1
14
15#ifndef __ASSEMBLY__
16enum {
17 STACKED = 0,
18 IP_DDR = 1,
19 COMBO_DDR = 2,
20 IP_SDR = 3,
21};
22#endif
23
24#define EARLY_INIT 1
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30
31
32
33#define SDRC_SHARING 0x00000100
34#define SDRC_MR_0_SDR 0x00000031
35
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39
40
41#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
42#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01
43#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201
44#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601
45
46#define DLL_OFFSET 0
47#define DLL_WRITEDDRCLKX2DIS 1
48#define DLL_ENADLL 1
49#define DLL_LOCKDLL 0
50#define DLL_DLLPHASE_72 0
51#define DLL_DLLPHASE_90 1
52
53
54#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
55 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
56
57
58#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27)
59#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22)
60#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18)
61#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15)
62#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12)
63#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9)
64#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6)
65#define ACTIM_CTRLA_TDAL(v) (v & 0x1F)
66
67#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
68 ACTIM_CTRLA_TRFC(trfc) | \
69 ACTIM_CTRLA_TRC(trc) | \
70 ACTIM_CTRLA_TRAS(tras) | \
71 ACTIM_CTRLA_TRP(trp) | \
72 ACTIM_CTRLA_TRCD(trcd) | \
73 ACTIM_CTRLA_TRRD(trrd) | \
74 ACTIM_CTRLA_TDPL(tdpl) | \
75 ACTIM_CTRLA_TDAL(tdal)
76
77
78#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16)
79#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12)
80#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8)
81#define ACTIM_CTRLB_TXSR(v) (v & 0xFF)
82
83#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
84 ACTIM_CTRLB_TWTR(twtr) | \
85 ACTIM_CTRLB_TCKE(tcke) | \
86 ACTIM_CTRLB_TXP(txp) | \
87 ACTIM_CTRLB_TXSR(txsr)
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92
93
94#define V_MCFG_RAMTYPE_DDR (0x1)
95#define V_MCFG_DEEPPD_EN (0x1 << 3)
96#define V_MCFG_B32NOT16_32 (0x1 << 4)
97#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6)
98#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8)
99#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
100#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20)
101#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
102#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24)
103
104
105#define MCFG(ramsize, raswidth) \
106 V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
107 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
108 V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
109 V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
110
111
112#define HYNIX_TDAL_165 6
113#define HYNIX_TDPL_165 3
114#define HYNIX_TRRD_165 2
115#define HYNIX_TRCD_165 3
116#define HYNIX_TRP_165 3
117#define HYNIX_TRAS_165 7
118#define HYNIX_TRC_165 10
119#define HYNIX_TRFC_165 21
120#define HYNIX_V_ACTIMA_165 \
121 ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
122 HYNIX_TRAS_165, HYNIX_TRP_165, \
123 HYNIX_TRCD_165, HYNIX_TRRD_165, \
124 HYNIX_TDPL_165, HYNIX_TDAL_165)
125
126#define HYNIX_TWTR_165 1
127#define HYNIX_TCKE_165 1
128#define HYNIX_TXP_165 2
129#define HYNIX_XSR_165 24
130#define HYNIX_V_ACTIMB_165 \
131 ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
132 HYNIX_TXP_165, HYNIX_XSR_165)
133
134#define HYNIX_RASWIDTH_165 13
135#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
136
137
138#define HYNIX_TDAL_200 6
139#define HYNIX_TDPL_200 3
140#define HYNIX_TRRD_200 2
141#define HYNIX_TRCD_200 4
142#define HYNIX_TRP_200 3
143#define HYNIX_TRAS_200 8
144#define HYNIX_TRC_200 11
145#define HYNIX_TRFC_200 18
146#define HYNIX_V_ACTIMA_200 \
147 ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
148 HYNIX_TRAS_200, HYNIX_TRP_200, \
149 HYNIX_TRCD_200, HYNIX_TRRD_200, \
150 HYNIX_TDPL_200, HYNIX_TDAL_200)
151
152#define HYNIX_TWTR_200 2
153#define HYNIX_TCKE_200 1
154#define HYNIX_TXP_200 1
155#define HYNIX_XSR_200 28
156#define HYNIX_V_ACTIMB_200 \
157 ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
158 HYNIX_TXP_200, HYNIX_XSR_200)
159
160#define HYNIX_RASWIDTH_200 14
161#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
162
163
164#define INFINEON_TDAL_165 6
165
166#define INFINEON_TDPL_165 3
167#define INFINEON_TRRD_165 2
168#define INFINEON_TRCD_165 3
169#define INFINEON_TRP_165 3
170#define INFINEON_TRAS_165 7
171#define INFINEON_TRC_165 10
172#define INFINEON_TRFC_165 12
173
174#define INFINEON_V_ACTIMA_165 \
175 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
176 INFINEON_TRAS_165, INFINEON_TRP_165, \
177 INFINEON_TRCD_165, INFINEON_TRRD_165, \
178 INFINEON_TDPL_165, INFINEON_TDAL_165)
179
180#define INFINEON_TWTR_165 1
181#define INFINEON_TCKE_165 2
182#define INFINEON_TXP_165 2
183#define INFINEON_XSR_165 20
184
185#define INFINEON_V_ACTIMB_165 \
186 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
187 INFINEON_TXP_165, INFINEON_XSR_165)
188
189
190#define MICRON_TDAL_165 6
191
192#define MICRON_TDPL_165 3
193#define MICRON_TRRD_165 2
194#define MICRON_TRCD_165 3
195#define MICRON_TRP_165 3
196#define MICRON_TRAS_165 7
197#define MICRON_TRC_165 10
198#define MICRON_TRFC_165 21
199
200#define MICRON_V_ACTIMA_165 \
201 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
202 MICRON_TRAS_165, MICRON_TRP_165, \
203 MICRON_TRCD_165, MICRON_TRRD_165, \
204 MICRON_TDPL_165, MICRON_TDAL_165)
205
206#define MICRON_TWTR_165 1
207#define MICRON_TCKE_165 1
208#define MICRON_XSR_165 23
209#define MICRON_TXP_165 5
210
211#define MICRON_V_ACTIMB_165 \
212 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
213 MICRON_TXP_165, MICRON_XSR_165)
214
215#define MICRON_RASWIDTH_165 13
216#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
217
218#define MICRON_BL_165 0x2
219#define MICRON_SIL_165 0x0
220#define MICRON_CASL_165 0x3
221#define MICRON_WBST_165 0x0
222#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
223 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
224 (MICRON_BL_165))
225
226
227#define MICRON_TDAL_200 6
228#define MICRON_TDPL_200 3
229#define MICRON_TRRD_200 2
230#define MICRON_TRCD_200 3
231#define MICRON_TRP_200 3
232#define MICRON_TRAS_200 8
233#define MICRON_TRC_200 11
234#define MICRON_TRFC_200 15
235#define MICRON_V_ACTIMA_200 \
236 ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
237 MICRON_TRAS_200, MICRON_TRP_200, \
238 MICRON_TRCD_200, MICRON_TRRD_200, \
239 MICRON_TDPL_200, MICRON_TDAL_200)
240
241#define MICRON_TWTR_200 2
242#define MICRON_TCKE_200 4
243#define MICRON_TXP_200 2
244#define MICRON_XSR_200 23
245#define MICRON_V_ACTIMB_200 \
246 ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
247 MICRON_TXP_200, MICRON_XSR_200)
248
249#define MICRON_RASWIDTH_200 14
250#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
251
252
253#define SAMSUNG_TDAL_165 5
254#define SAMSUNG_TDPL_165 2
255#define SAMSUNG_TRRD_165 2
256#define SAMSUNG_TRCD_165 3
257#define SAMSUNG_TRP_165 3
258#define SAMSUNG_TRAS_165 7
259#define SAMSUNG_TRC_165 10
260#define SAMSUNG_TRFC_165 12
261
262#define SAMSUNG_V_ACTIMA_165 \
263 ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
264 SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
265 SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
266 SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
267
268#define SAMSUNG_TWTR_165 1
269#define SAMSUNG_TCKE_165 2
270#define SAMSUNG_XSR_165 20
271#define SAMSUNG_TXP_165 5
272
273#define SAMSUNG_V_ACTIMB_165 \
274 ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
275 SAMSUNG_TXP_165, SAMSUNG_XSR_165)
276
277#define SAMSUNG_RASWIDTH_165 14
278#define SAMSUNG_V_MCFG_165(size) \
279 V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
280 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
281 V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
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283
284
285#define SAMSUNG_BL_165 0x2
286#define SAMSUNG_SIL_165 0x0
287#define SAMSUNG_CASL_165 0x3
288#define SAMSUNG_WBST_165 0x0
289#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
290 (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
291 (SAMSUNG_BL_165))
292
293#define SAMSUNG_SHARING 0x00003700
294
295
296#define NUMONYX_TDAL_165 6
297
298#define NUMONYX_TDPL_165 3
299#define NUMONYX_TRRD_165 2
300#define NUMONYX_TRCD_165 4
301#define NUMONYX_TRP_165 3
302#define NUMONYX_TRAS_165 7
303#define NUMONYX_TRC_165 10
304#define NUMONYX_TRFC_165 24
305
306#define NUMONYX_V_ACTIMA_165 \
307 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
308 NUMONYX_TRAS_165, NUMONYX_TRP_165, \
309 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
310 NUMONYX_TDPL_165, NUMONYX_TDAL_165)
311
312#define NUMONYX_TWTR_165 2
313#define NUMONYX_TCKE_165 2
314#define NUMONYX_TXP_165 3
315#define NUMONYX_XSR_165 34
316
317#define NUMONYX_V_ACTIMB_165 \
318 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
319 NUMONYX_TXP_165, NUMONYX_XSR_165)
320
321#define NUMONYX_RASWIDTH_165 15
322#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
323
324
325#define NUMONYX_TDAL_200 6
326
327#define NUMONYX_TDPL_200 3
328#define NUMONYX_TRRD_200 2
329#define NUMONYX_TRCD_200 4
330#define NUMONYX_TRP_200 3
331#define NUMONYX_TRAS_200 8
332#define NUMONYX_TRC_200 11
333#define NUMONYX_TRFC_200 28
334
335#define NUMONYX_V_ACTIMA_200 \
336 ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
337 NUMONYX_TRAS_200, NUMONYX_TRP_200, \
338 NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
339 NUMONYX_TDPL_200, NUMONYX_TDAL_200)
340
341#define NUMONYX_TWTR_200 2
342#define NUMONYX_TCKE_200 2
343#define NUMONYX_TXP_200 3
344#define NUMONYX_XSR_200 40
345
346#define NUMONYX_V_ACTIMB_200 \
347 ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
348 NUMONYX_TXP_200, NUMONYX_XSR_200)
349
350#define NUMONYX_RASWIDTH_200 15
351#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
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389
390#define GPMC_SIZE_256M 0x0
391#define GPMC_SIZE_128M 0x8
392#define GPMC_SIZE_64M 0xC
393#define GPMC_SIZE_32M 0xE
394#define GPMC_SIZE_16M 0xF
395
396#define GPMC_BASEADDR_MASK 0x3F
397
398#define GPMC_CS_ENABLE 0x1
399
400#define M_NAND_GPMC_CONFIG1 0x00001800
401#define M_NAND_GPMC_CONFIG2 0x00141400
402#define M_NAND_GPMC_CONFIG3 0x00141400
403#define M_NAND_GPMC_CONFIG4 0x0F010F01
404#define M_NAND_GPMC_CONFIG5 0x010C1414
405#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
406#define M_NAND_GPMC_CONFIG7 0x00000C44
407
408#define STNOR_GPMC_CONFIG1 0x3
409#define STNOR_GPMC_CONFIG2 0x00151501
410#define STNOR_GPMC_CONFIG3 0x00060602
411#define STNOR_GPMC_CONFIG4 0x11091109
412#define STNOR_GPMC_CONFIG5 0x01141F1F
413#define STNOR_GPMC_CONFIG6 0x000004c4
414
415#define SIBNOR_GPMC_CONFIG1 0x1200
416#define SIBNOR_GPMC_CONFIG2 0x001f1f00
417#define SIBNOR_GPMC_CONFIG3 0x00080802
418#define SIBNOR_GPMC_CONFIG4 0x1C091C09
419#define SIBNOR_GPMC_CONFIG5 0x01131F1F
420#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
421
422#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
423#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
424#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
425#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
426#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
427#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
428
429#define MPDB_GPMC_CONFIG1 0x00011000
430#define MPDB_GPMC_CONFIG2 0x001f1f01
431#define MPDB_GPMC_CONFIG3 0x00080803
432#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
433#define MPDB_GPMC_CONFIG5 0x041f1F1F
434#define MPDB_GPMC_CONFIG6 0x1F0F04C4
435
436#define P2_GPMC_CONFIG1 0x0
437#define P2_GPMC_CONFIG2 0x0
438#define P2_GPMC_CONFIG3 0x0
439#define P2_GPMC_CONFIG4 0x0
440#define P2_GPMC_CONFIG5 0x0
441#define P2_GPMC_CONFIG6 0x0
442
443#define ONENAND_GPMC_CONFIG1 0x00001200
444#define ONENAND_GPMC_CONFIG2 0x000F0F01
445#define ONENAND_GPMC_CONFIG3 0x00030301
446#define ONENAND_GPMC_CONFIG4 0x0F040F04
447#define ONENAND_GPMC_CONFIG5 0x010F1010
448#define ONENAND_GPMC_CONFIG6 0x1F060000
449
450#define NET_GPMC_CONFIG1 0x00001000
451#define NET_GPMC_CONFIG2 0x001e1e01
452#define NET_GPMC_CONFIG3 0x00080300
453#define NET_GPMC_CONFIG4 0x1c091c09
454#define NET_GPMC_CONFIG5 0x04181f1f
455#define NET_GPMC_CONFIG6 0x00000FCF
456#define NET_GPMC_CONFIG7 0x00000f6c
457
458
459#define NET_LAN9221_GPMC_CONFIG1 0x00001000
460#define NET_LAN9221_GPMC_CONFIG2 0x00060700
461#define NET_LAN9221_GPMC_CONFIG3 0x00020201
462#define NET_LAN9221_GPMC_CONFIG4 0x06000700
463#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
464#define NET_LAN9221_GPMC_CONFIG6 0x87030000
465#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
466
467
468
469#define GPMC_MAX_CS 8
470
471#define GPMC_MAX_REG 7
472
473#define DBG_MPDB 6
474#define DBG_MPDB_BASE DEBUG_BASE
475
476#ifndef __ASSEMBLY__
477
478
479void mem_init(void);
480
481u32 is_mem_sdr(void);
482u32 mem_ok(u32 cs);
483
484u32 get_sdr_cs_size(u32);
485u32 get_sdr_cs_offset(u32);
486
487#endif
488
489#endif
490