LXR uboot/arch/arm/mach-kirkwood/include/mach/cpu.h

   1/*
   2 * (C) Copyright 2009
   3 * Marvell Semiconductor <www.marvell.com>
   4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#ifndef _KWCPU_H
  10#define _KWCPU_H
  11
  12#include <asm/system.h>
  13
  14#ifndef __ASSEMBLY__
  15
  16#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
  17                        | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
  18
  19#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)      \
  20                ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
  21
  22#define KW_REG_PCIE_DEVID               (KW_REG_PCIE_BASE + 0x00)
  23#define KW_REG_PCIE_REVID               (KW_REG_PCIE_BASE + 0x08)
  24#define KW_REG_DEVICE_ID                (KW_MPP_BASE + 0x34)
  25#define KW_REG_SYSRST_CNT               (KW_MPP_BASE + 0x50)
  26#define SYSRST_CNT_1SEC_VAL             (25*1000000)
  27#define KW_REG_MPP_OUT_DRV_REG          (KW_MPP_BASE + 0xE0)
  28
  29enum memory_bank {
  30        BANK0,
  31        BANK1,
  32        BANK2,
  33        BANK3
  34};
  35
  36enum kwcpu_winen {
  37        KWCPU_WIN_DISABLE,
  38        KWCPU_WIN_ENABLE
  39};
  40
  41enum kwcpu_target {
  42        KWCPU_TARGET_RESERVED,
  43        KWCPU_TARGET_MEMORY,
  44        KWCPU_TARGET_1RESERVED,
  45        KWCPU_TARGET_SASRAM,
  46        KWCPU_TARGET_PCIE
  47};
  48
  49enum kwcpu_attrib {
  50        KWCPU_ATTR_SASRAM = 0x01,
  51        KWCPU_ATTR_DRAM_CS0 = 0x0e,
  52        KWCPU_ATTR_DRAM_CS1 = 0x0d,
  53        KWCPU_ATTR_DRAM_CS2 = 0x0b,
  54        KWCPU_ATTR_DRAM_CS3 = 0x07,
  55        KWCPU_ATTR_NANDFLASH = 0x2f,
  56        KWCPU_ATTR_SPIFLASH = 0x1e,
  57        KWCPU_ATTR_BOOTROM = 0x1d,
  58        KWCPU_ATTR_PCIE_IO = 0xe0,
  59        KWCPU_ATTR_PCIE_MEM = 0xe8
  60};
  61
  62/*
  63 * Default Device Address MAP BAR values
  64 */
  65#define KW_DEFADR_PCI_MEM       0x90000000
  66#define KW_DEFADR_PCI_IO        0xC0000000
  67#define KW_DEFADR_PCI_IO_REMAP  0xC0000000
  68#define KW_DEFADR_SASRAM        0xC8010000
  69#define KW_DEFADR_NANDF         0xD8000000
  70#define KW_DEFADR_SPIF          0xE8000000
  71#define KW_DEFADR_BOOTROM       0xF8000000
  72
  73/*
  74 * read feroceon/sheeva core extra feature register
  75 * using co-proc instruction
  76 */
  77static inline unsigned int readfr_extra_feature_reg(void)
  78{
  79        unsigned int val;
  80        asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
  81                        (val)::"cc");
  82        return val;
  83}
  84
  85/*
  86 * write feroceon/sheeva core extra feature register
  87 * using co-proc instruction
  88 */
  89static inline void writefr_extra_feature_reg(unsigned int val)
  90{
  91        asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
  92                        (val):"cc");
  93        isb();
  94}
  95
  96/*
  97 * MBus-L to Mbus Bridge Registers
  98 * Ref: Datasheet sec:A.3
  99 */
 100struct kwwin_registers {
 101        u32 ctrl;
 102        u32 base;
 103        u32 remap_lo;
 104        u32 remap_hi;
 105};
 106
 107/*
 108 * CPU control and status Registers
 109 * Ref: Datasheet sec:A.3.2
 110 */
 111struct kwcpu_registers {
 112        u32 config;     /*0x20100 */
 113        u32 ctrl_stat;  /*0x20104 */
 114        u32 rstoutn_mask; /* 0x20108 */
 115        u32 sys_soft_rst; /* 0x2010C */
 116        u32 ahb_mbus_cause_irq; /* 0x20110 */
 117        u32 ahb_mbus_mask_irq; /* 0x20114 */
 118        u32 pad1[2];
 119        u32 ftdll_config; /* 0x20120 */
 120        u32 pad2;
 121        u32 l2_cfg;     /* 0x20128 */
 122};
 123
 124/*
 125 * GPIO Registers
 126 * Ref: Datasheet sec:A.19
 127 */
 128struct kwgpio_registers {
 129        u32 dout;
 130        u32 oe;
 131        u32 blink_en;
 132        u32 din_pol;
 133        u32 din;
 134        u32 irq_cause;
 135        u32 irq_mask;
 136        u32 irq_level;
 137};
 138
 139/*
 140 * functions
 141 */
 142unsigned char get_random_hex(void);
 143unsigned int mvebu_sdram_bar(enum memory_bank bank);
 144unsigned int mvebu_sdram_bs(enum memory_bank bank);
 145void mvebu_sdram_size_adjust(enum memory_bank bank);
 146int kw_config_adr_windows(void);
 147void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 148                unsigned int gpp0_oe, unsigned int gpp1_oe);
 149int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
 150                unsigned int mpp16_23, unsigned int mpp24_31,
 151                unsigned int mpp32_39, unsigned int mpp40_47,
 152                unsigned int mpp48_55);
 153unsigned int kw_winctrl_calcsize(unsigned int sizeval);
 154#endif /* __ASSEMBLY__ */
 155#endif /* _KWCPU_H */
 156