LXR uboot/arch/m68k/include/asm/coldfire/qspi.h

   1/*
   2 * Queue Serial Peripheral Interface Memory Map
   3 *
   4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#ifndef __QSPI_H__
  11#define __QSPI_H__
  12
  13/* QSPI module registers */
  14typedef struct qspi_ctrl {
  15        u16 mr;                 /* 0x00 Mode */
  16        u16 res1;
  17        u16 dlyr;               /* 0x04 Delay */
  18        u16 res2;
  19        u16 wr;                 /* 0x08 Wrap */
  20        u16 res3;
  21        u16 ir;                 /* 0x0C Interrupt */
  22        u16 res4;
  23        u16 ar;                 /* 0x10 Address */
  24        u16 res5;
  25        u16 dr;                 /* 0x14 Data */
  26        u16 res6;
  27} qspi_t;
  28
  29/* MR */
  30#define QSPI_QMR_MSTR                   (0x8000)
  31#define QSPI_QMR_DOHIE                  (0x4000)
  32#define QSPI_QMR_BITS(x)                (((x)&0x000F)<<10)
  33#define QSPI_QMR_BITS_MASK              (0xC3FF)
  34#define QSPI_QMR_BITS_8                 (0x2000)
  35#define QSPI_QMR_BITS_9                 (0x2400)
  36#define QSPI_QMR_BITS_10                (0x2800)
  37#define QSPI_QMR_BITS_11                (0x2C00)
  38#define QSPI_QMR_BITS_12                (0x3000)
  39#define QSPI_QMR_BITS_13                (0x3400)
  40#define QSPI_QMR_BITS_14                (0x3800)
  41#define QSPI_QMR_BITS_15                (0x3C00)
  42#define QSPI_QMR_BITS_16                (0x0000)
  43#define QSPI_QMR_CPOL                   (0x0200)
  44#define QSPI_QMR_CPHA                   (0x0100)
  45#define QSPI_QMR_BAUD(x)                ((x)&0x00FF)
  46#define QSPI_QMR_BAUD_MASK              (0xFF00)
  47
  48/* DLYR */
  49#define QSPI_QDLYR_SPE                  (0x8000)
  50#define QSPI_QDLYR_QCD(x)               (((x)&0x007F)<<8)
  51#define QSPI_QDLYR_QCD_MASK             (0x80FF)
  52#define QSPI_QDLYR_DTL(x)               ((x)&0x00FF)
  53#define QSPI_QDLYR_DTL_MASK             (0xFF00)
  54
  55/* WR */
  56#define QSPI_QWR_HALT                   (0x8000)
  57#define QSPI_QWR_WREN                   (0x4000)
  58#define QSPI_QWR_WRTO                   (0x2000)
  59#define QSPI_QWR_CSIV                   (0x1000)
  60#define QSPI_QWR_ENDQP(x)               (((x)&0x000F)<<8)
  61#define QSPI_QWR_ENDQP_MASK             (0xF0FF)
  62#define QSPI_QWR_CPTQP(x)               (((x)&0x000F)<<4)
  63#define QSPI_QWR_CPTQP_MASK             (0xFF0F)
  64#define QSPI_QWR_NEWQP(x)               ((x)&0x000F)
  65#define QSPI_QWR_NEWQP_MASK             (0xFFF0)
  66
  67/* IR */
  68#define QSPI_QIR_WCEFB                  (0x8000)
  69#define QSPI_QIR_ABRTB                  (0x4000)
  70#define QSPI_QIR_ABRTL                  (0x1000)
  71#define QSPI_QIR_WCEFE                  (0x0800)
  72#define QSPI_QIR_ABRTE                  (0x0400)
  73#define QSPI_QIR_SPIFE                  (0x0100)
  74#define QSPI_QIR_WCEF                   (0x0008)
  75#define QSPI_QIR_ABRT                   (0x0004)
  76#define QSPI_QIR_SPIF                   (0x0001)
  77
  78/* AR */
  79#define QSPI_QAR_ADDR(x)                ((x)&0x003F)
  80#define QSPI_QAR_ADDR_MASK              (0xFFC0)
  81#define QSPI_QAR_TRANS                  (0x0000)
  82#define QSPI_QAR_RECV                   (0x0010)
  83#define QSPI_QAR_CMD                    (0x0020)
  84
  85/* DR with RAM command word definitions */
  86#define QSPI_QDR_CONT                   (0x8000)
  87#define QSPI_QDR_BITSE                  (0x4000)
  88#define QSPI_QDR_DT                     (0x2000)
  89#define QSPI_QDR_DSCK                   (0x1000)
  90#define QSPI_QDR_QSPI_CS3               (0x0800)
  91#define QSPI_QDR_QSPI_CS2               (0x0400)
  92#define QSPI_QDR_QSPI_CS1               (0x0200)
  93#define QSPI_QDR_QSPI_CS0               (0x0100)
  94
  95#endif                          /* __QSPI_H__ */
  96