LXR uboot/board/Marvell/db-88f6820-gp/db-88f6820-gp.c

   1/*
   2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <miiphy.h>
  10#include <netdev.h>
  11#include <asm/io.h>
  12#include <asm/arch/cpu.h>
  13#include <asm/arch/soc.h>
  14
  15#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
  16#include <../serdes/a38x/high_speed_env_spec.h>
  17
  18DECLARE_GLOBAL_DATA_PTR;
  19
  20#define ETH_PHY_CTRL_REG                0
  21#define ETH_PHY_CTRL_POWER_DOWN_BIT     11
  22#define ETH_PHY_CTRL_POWER_DOWN_MASK    (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
  23
  24/*
  25 * Those values and defines are taken from the Marvell U-Boot version
  26 * "u-boot-2013.01-2014_T3.0"
  27 */
  28#define DB_GP_88F68XX_GPP_OUT_ENA_LOW                                   \
  29        (~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |  \
  30           BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |  \
  31           BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  32#define DB_GP_88F68XX_GPP_OUT_ENA_MID                                   \
  33        (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |       \
  34           BIT(16) | BIT(17) | BIT(18)))
  35
  36#define DB_GP_88F68XX_GPP_OUT_VAL_LOW   0x0
  37#define DB_GP_88F68XX_GPP_OUT_VAL_MID   0x0
  38#define DB_GP_88F68XX_GPP_POL_LOW       0x0
  39#define DB_GP_88F68XX_GPP_POL_MID       0x0
  40
  41/* IO expander on Marvell GP board includes e.g. fan enabling */
  42struct marvell_io_exp {
  43        u8 chip;
  44        u8 addr;
  45        u8 val;
  46};
  47
  48static struct marvell_io_exp io_exp[] = {
  49        { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  50        { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  51        { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  52        { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  53        { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
  54        { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
  55        { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  56        { 0x21, 3, 0xC0 }  /* Output Data, register#1 */
  57};
  58
  59static struct serdes_map board_serdes_map[] = {
  60        {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  61        {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  62        {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  63        {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  64        {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  65        {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  66};
  67
  68int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  69{
  70        *serdes_map_array = board_serdes_map;
  71        *count = ARRAY_SIZE(board_serdes_map);
  72        return 0;
  73}
  74
  75/*
  76 * Define the DDR layout / topology here in the board file. This will
  77 * be used by the DDR3 init code in the SPL U-Boot version to configure
  78 * the DDR3 controller.
  79 */
  80static struct hws_topology_map board_topology_map = {
  81        0x1, /* active interfaces */
  82        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  83        { { { {0x1, 0, 0, 0},
  84              {0x1, 0, 0, 0},
  85              {0x1, 0, 0, 0},
  86              {0x1, 0, 0, 0},
  87              {0x1, 0, 0, 0} },
  88            SPEED_BIN_DDR_1866L,        /* speed_bin */
  89            BUS_WIDTH_8,                /* memory_width */
  90            MEM_4G,                     /* mem_size */
  91            DDR_FREQ_800,               /* frequency */
  92            0, 0,                       /* cas_l cas_wl */
  93            HWS_TEMP_LOW} },            /* temperature */
  94        5,                              /* Num Of Bus Per Interface*/
  95        BUS_MASK_32BIT                  /* Busses mask */
  96};
  97
  98struct hws_topology_map *ddr3_get_topology_map(void)
  99{
 100        /* Return the board topology as defined in the board code */
 101        return &board_topology_map;
 102}
 103
 104int board_early_init_f(void)
 105{
 106        /* Configure MPP */
 107        writel(0x11111111, MVEBU_MPP_BASE + 0x00);
 108        writel(0x11111111, MVEBU_MPP_BASE + 0x04);
 109        writel(0x11244011, MVEBU_MPP_BASE + 0x08);
 110        writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
 111        writel(0x22200002, MVEBU_MPP_BASE + 0x10);
 112        writel(0x30042022, MVEBU_MPP_BASE + 0x14);
 113        writel(0x55550555, MVEBU_MPP_BASE + 0x18);
 114        writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
 115
 116        /* Set GPP Out value */
 117        writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 118        writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 119
 120        /* Set GPP Polarity */
 121        writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 122        writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 123
 124        /* Set GPP Out Enable */
 125        writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 126        writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 127
 128        return 0;
 129}
 130
 131int board_init(void)
 132{
 133        int i;
 134
 135        /* adress of boot parameters */
 136        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 137
 138        /* Init I2C IO expanders */
 139        for (i = 0; i < ARRAY_SIZE(io_exp); i++)
 140                i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
 141
 142        return 0;
 143}
 144
 145int checkboard(void)
 146{
 147        puts("Board: Marvell DB-88F6820-GP\n");
 148
 149        return 0;
 150}
 151
 152int board_eth_init(bd_t *bis)
 153{
 154        cpu_eth_init(bis); /* Built in controller(s) come first */
 155        return pci_eth_init(bis);
 156}
 157