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13#include <asm/arch/clock.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <linux/errno.h>
18#include <asm/gpio.h>
19#include <asm/imx-common/iomux-v3.h>
20#include <asm/imx-common/boot_mode.h>
21#include <asm/imx-common/mxc_i2c.h>
22#include <asm/imx-common/video.h>
23#include <mmc.h>
24#include <fsl_esdhc.h>
25#include <miiphy.h>
26#include <netdev.h>
27#include <asm/arch/mxc_hdmi.h>
28#include <asm/arch/crm_regs.h>
29#include <linux/fb.h>
30#include <ipu_pixfmt.h>
31#include <asm/io.h>
32#include <asm/arch/sys_proto.h>
33#include <pwm.h>
34
35struct i2c_pads_info i2c_pad_info3 = {
36 .scl = {
37 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
38 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
39 .gp = IMX_GPIO_NR(3, 17)
40 },
41 .sda = {
42 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
43 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
44 .gp = IMX_GPIO_NR(3, 18)
45 }
46};
47
48iomux_v3_cfg_t const uart1_pads[] = {
49 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
50 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51};
52
53iomux_v3_cfg_t const uart5_pads[] = {
54 MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
55 MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56};
57
58iomux_v3_cfg_t const gpio_pads[] = {
59
60 MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
61
62 MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
63
64 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
65
66 MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
67
68 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
69
70 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
71
72 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
73
74 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
75
76 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
77
78 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
79};
80
81static iomux_v3_cfg_t const misc_pads[] = {
82 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
83
84 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
85 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
86};
87
88iomux_v3_cfg_t const enet_pads[] = {
89 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
90 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
99};
100
101static void setup_iomux_enet(void)
102{
103 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
104
105 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
106
107
108 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
109}
110
111static iomux_v3_cfg_t const backlight_pads[] = {
112 MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
114 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
115};
116
117iomux_v3_cfg_t const ecspi4_pads[] = {
118 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
119 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
120 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
121 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
122};
123
124static iomux_v3_cfg_t const display_pads[] = {
125 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
126 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
127 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
128 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
129 MX6_PAD_DI0_PIN4__GPIO4_IO20,
130 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
131 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
132 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
133 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
134 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
135 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
136 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
137 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
138 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
139 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
140 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
141 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
142 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
143 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
144 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
145 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
146 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
147 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
148 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
149 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
150 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
151 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
152 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
153 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
154};
155
156int board_spi_cs_gpio(unsigned bus, unsigned cs)
157{
158 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
159 ? (IMX_GPIO_NR(3, 20)) : -1;
160}
161
162static void setup_spi(void)
163{
164 int i;
165
166 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
167 for (i = 0; i < 3; i++)
168 enable_spi_clk(true, i);
169
170
171 gpio_direction_output(ECSPI4_CS1, 1);
172}
173
174static void setup_iomux_uart(void)
175{
176 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
177}
178
179int board_eth_init(bd_t *bis)
180{
181 struct iomuxc *iomuxc_regs =
182 (struct iomuxc *)IOMUXC_BASE_ADDR;
183 int ret;
184
185
186 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
187
188 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
189 if (ret)
190 return ret;
191
192 setup_iomux_enet();
193 return cpu_eth_init(bis);
194}
195
196static void enable_lvds(struct display_info_t const *dev)
197{
198 imx_iomux_v3_setup_multiple_pads(
199 display_pads,
200 ARRAY_SIZE(display_pads));
201 imx_iomux_v3_setup_multiple_pads(
202 backlight_pads,
203 ARRAY_SIZE(backlight_pads));
204
205
206 if (pwm_init(2, 0, 0))
207 goto error;
208
209 if (pwm_config(2, 500, 3000))
210 goto error;
211 if (pwm_enable(2))
212 goto error;
213 return;
214
215error:
216 puts("error init pwm for backlight\n");
217 return;
218}
219
220static void setup_display(void)
221{
222 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
223 int reg;
224
225 enable_ipu_clock();
226
227 reg = readl(&mxc_ccm->cs2cdr);
228
229 reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
230 reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
231 writel(reg, &mxc_ccm->cs2cdr);
232
233 imx_iomux_v3_setup_multiple_pads(backlight_pads,
234 ARRAY_SIZE(backlight_pads));
235}
236
237static void setup_iomux_gpio(void)
238{
239 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
240}
241
242int board_early_init_f(void)
243{
244 setup_iomux_uart();
245 setup_iomux_gpio();
246
247 setup_display();
248 return 0;
249}
250
251
252static void setup_i2c4(void)
253{
254
255 gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
256 gpio_direction_input(IMX_GPIO_NR(1, 7));
257 gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
258 gpio_direction_input(IMX_GPIO_NR(1, 8));
259}
260
261static void setup_board_gpio(void)
262{
263
264 gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
265 gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
266
267 gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
268 gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
269 gpio_request(IMX_GPIO_NR(1, 4), "LED red");
270 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
271 gpio_request(IMX_GPIO_NR(1, 5), "LED green");
272 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
273 gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
274 gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
275}
276
277static void setup_board_spi(void)
278{
279}
280
