LXR uboot/board/armltd/vexpress64/vexpress64.c

   1/*
   2 * (C) Copyright 2013
   3 * David Feng <fenghua@phytium.com.cn>
   4 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8#include <common.h>
   9#include <malloc.h>
  10#include <errno.h>
  11#include <netdev.h>
  12#include <asm/io.h>
  13#include <linux/compiler.h>
  14#include <dm/platdata.h>
  15#include <dm/platform_data/serial_pl01x.h>
  16#include "pcie.h"
  17#include <asm/armv8/mmu.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21static const struct pl01x_serial_platdata serial_platdata = {
  22        .base = V2M_UART0,
  23        .type = TYPE_PL011,
  24        .clock = CONFIG_PL011_CLOCK,
  25};
  26
  27U_BOOT_DEVICE(vexpress_serials) = {
  28        .name = "serial_pl01x",
  29        .platdata = &serial_platdata,
  30};
  31
  32static struct mm_region vexpress64_mem_map[] = {
  33        {
  34                .virt = 0x0UL,
  35                .phys = 0x0UL,
  36                .size = 0x80000000UL,
  37                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  38                         PTE_BLOCK_NON_SHARE |
  39                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
  40        }, {
  41                .virt = 0x80000000UL,
  42                .phys = 0x80000000UL,
  43                .size = 0xff80000000UL,
  44                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  45                         PTE_BLOCK_INNER_SHARE
  46        }, {
  47                /* List terminator */
  48                0,
  49        }
  50};
  51
  52struct mm_region *mem_map = vexpress64_mem_map;
  53
  54/* This function gets replaced by platforms supporting PCIe.
  55 * The replacement function, eg. on Juno, initialises the PCIe bus.
  56 */
  57__weak void vexpress64_pcie_init(void)
  58{
  59}
  60
  61int board_init(void)
  62{
  63        vexpress64_pcie_init();
  64        return 0;
  65}
  66
  67int dram_init(void)
  68{
  69        gd->ram_size = PHYS_SDRAM_1_SIZE;
  70        return 0;
  71}
  72
  73void dram_init_banksize(void)
  74{
  75        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  76        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  77#ifdef PHYS_SDRAM_2
  78        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  79        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  80#endif
  81}
  82
  83/*
  84 * Board specific reset that is system reset.
  85 */
  86void reset_cpu(ulong addr)
  87{
  88}
  89
  90/*
  91 * Board specific ethernet initialization routine.
  92 */
  93int board_eth_init(bd_t *bis)
  94{
  95        int rc = 0;
  96#ifdef CONFIG_SMC91111
  97        rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  98#endif
  99#ifdef CONFIG_SMC911X
 100        rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 101#endif
 102        return rc;
 103}
 104