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6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
13#include <fdt_support.h>
14#include <libfdt.h>
15#include <fsl-mc/fsl_mc.h>
16#include <environment.h>
17#include <asm/arch/soc.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_init(void)
22{
23 init_final_memctl_regs();
24
25#ifdef CONFIG_ENV_IS_NOWHERE
26 gd->env_addr = (ulong)&default_environment[0];
27#endif
28
29 return 0;
30}
31
32int board_early_init_f(void)
33{
34 fsl_lsch3_early_init_f();
35 return 0;
36}
37
38void detail_board_ddr_info(void)
39{
40 puts("\nDDR ");
41 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
42 print_ddr_info(0);
43#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
44 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
45 puts("\nDP-DDR ");
46 print_size(gd->bd->bi_dram[2].size, "");
47 print_ddr_info(CONFIG_DP_DDR_CTRL);
48 }
49#endif
50}
51
52int dram_init(void)
53{
54 gd->ram_size = initdram(0);
55
56 return 0;
57}
58
59#if defined(CONFIG_ARCH_MISC_INIT)
60int arch_misc_init(void)
61{
62 return 0;
63}
64#endif
65
66int board_eth_init(bd_t *bis)
67{
68 int error = 0;
69
70#ifdef CONFIG_SMC91111
71 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
72#endif
73
74#ifdef CONFIG_FSL_MC_ENET
75 error = cpu_eth_init(bis);
76#endif
77 return error;
78}
79
80#ifdef CONFIG_FSL_MC_ENET
81void fdt_fixup_board_enet(void *fdt)
82{
83 int offset;
84
85 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
86
87
88
89
90
91 if (offset < 0)
92 offset = fdt_path_offset(fdt, "/fsl-mc");
93
94 if (offset < 0) {
95 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
96 __func__, offset);
97 return;
98 }
99
100 if (get_mc_boot_status() == 0)
101 fdt_status_okay(fdt, offset);
102 else
103 fdt_status_fail(fdt, offset);
104}
105
106void board_quiesce_devices(void)
107{
108 fsl_mc_ldpaa_exit(gd->bd);
109}
110#endif
111
112#ifdef CONFIG_OF_BOARD_SETUP
113int ft_board_setup(void *blob, bd_t *bd)
114{
115 u64 base[CONFIG_NR_DRAM_BANKS];
116 u64 size[CONFIG_NR_DRAM_BANKS];
117
118 ft_cpu_setup(blob, bd);
119
120
121 base[0] = gd->bd->bi_dram[0].start;
122 size[0] = gd->bd->bi_dram[0].size;
123 base[1] = gd->bd->bi_dram[1].start;
124 size[1] = gd->bd->bi_dram[1].size;
125
126 fdt_fixup_memory_banks(blob, base, size, 2);
127
128#ifdef CONFIG_FSL_MC_ENET
129 fdt_fixup_board_enet(blob);
130#endif
131
132 return 0;
133}
134#endif
135