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7#include <common.h>
8#include <asm/processor.h>
9#include <asm/mmu.h>
10#include <asm/cache.h>
11#include <asm/immap_85xx.h>
12#include <asm/io.h>
13#include <miiphy.h>
14#include <libfdt.h>
15#include <fdt_support.h>
16#include <fsl_mdio.h>
17#include <tsec.h>
18#include <mmc.h>
19#include <netdev.h>
20#include <pci.h>
21#include <asm/fsl_serdes.h>
22#include <fsl_ifc.h>
23#include <asm/fsl_pci.h>
24#include <hwconfig.h>
25#include <i2c.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define GPIO4_PCIE_RESET_SET 0x08000000
30#define MUX_CPLD_CAN_UART 0x00
31#define MUX_CPLD_TDM 0x01
32#define MUX_CPLD_SPICS0_FLASH 0x00
33#define MUX_CPLD_SPICS0_SLIC 0x02
34#define PMUXCR1_IFC_MASK 0x00ffff00
35#define PMUXCR1_SDHC_MASK 0x00fff000
36#define PMUXCR1_SDHC_ENABLE 0x00555000
37
38enum {
39 MUX_TYPE_IFC,
40 MUX_TYPE_SDHC,
41 MUX_TYPE_SPIFLASH,
42 MUX_TYPE_TDM,
43 MUX_TYPE_CAN,
44 MUX_TYPE_CS0_NOR,
45 MUX_TYPE_CS0_NAND,
46};
47
48enum {
49 I2C_READ_BANK,
50 I2C_READ_PCB_VER,
51};
52
53static uint sd_ifc_mux;
54
55struct cpld_data {
56 u8 cpld_ver;
57#if defined(CONFIG_TARGET_P1010RDB_PA)
58 u8 pcba_ver;
59 u8 twindie_ddr3;
60 u8 res1[6];
61 u8 bank_sel;
62 u8 res2[5];
63 u8 usb2_sel;
64 u8 res3[1];
65 u8 porsw_sel;
66 u8 tdm_can_sel;
67 u8 spi_cs0_sel;
68 u8 por0;
69 u8 por1;
70 u8 por2;
71 u8 por3;
72#elif defined(CONFIG_TARGET_P1010RDB_PB)
73 u8 rom_loc;
74#endif
75};
76
77int board_early_init_f(void)
78{
79 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
80 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
81
82 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
83
84
85
86 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
87 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
88
89 return 0;
90}
91
92int board_early_init_r(void)
93{
94 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
95 int flash_esel = find_tlb_idx((void *)flashbase, 1);
96
97
98
99
100
101
102
103 flush_dcache();
104 invalidate_icache();
105
106 if (flash_esel == -1) {
107
108 puts("Error: Could not find TLB for FLASH BASE\n");
109 flash_esel = 2;
110 } else {
111
112 disable_tlb(flash_esel);
113 }
114
115 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
117 0, flash_esel, BOOKE_PAGESZ_16M, 1);
118
119 set_tlb(1, flashbase + 0x1000000,
120 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
121 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
122 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
123 return 0;
124}
125
126#ifdef CONFIG_PCI
127void pci_init_board(void)
128{
129 fsl_pcie_init_board(0);
130}
131#endif
132
133int config_board_mux(int ctrl_type)
134{
135 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
136 u8 tmp;
137
138#if defined(CONFIG_TARGET_P1010RDB_PA)
139 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
140
141 switch (ctrl_type) {
142 case MUX_TYPE_IFC:
143 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
144 tmp = 0xf0;
145 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
146 tmp = 0x01;
147 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
148 sd_ifc_mux = MUX_TYPE_IFC;
149 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
150 break;
151 case MUX_TYPE_SDHC:
152 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
153 tmp = 0xf0;
154 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
155 tmp = 0x05;
156 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
157 sd_ifc_mux = MUX_TYPE_SDHC;
158 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
159 PMUXCR1_SDHC_ENABLE);
160 break;
161 case MUX_TYPE_SPIFLASH:
162 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
163 break;
164 case MUX_TYPE_TDM:
165 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
166 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
167 break;
168 case MUX_TYPE_CAN:
169 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
170 break;
171 default:
172 break;
173 }
174#elif defined(CONFIG_TARGET_P1010RDB_PB)
175 uint orig_bus = i2c_get_bus_num();
176 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
177
178 switch (ctrl_type) {
179 case MUX_TYPE_IFC:
180 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
181 clrbits_8(&tmp, 0x04);
182 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
183 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
184 clrbits_8(&tmp, 0x04);
185 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
186 sd_ifc_mux = MUX_TYPE_IFC;
187 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
188 break;
189 case MUX_TYPE_SDHC:
190 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
191 setbits_8(&tmp, 0x04);
192 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
193 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
194 clrbits_8(&tmp, 0x04);
195 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
196 sd_ifc_mux = MUX_TYPE_SDHC;
197 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
198 PMUXCR1_SDHC_ENABLE);
199 break;
200 case MUX_TYPE_SPIFLASH:
201 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
202 clrbits_8(&tmp, 0x80);
203 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
204 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
205 clrbits_8(&tmp, 0x80);
206 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
207 break;
208 case MUX_TYPE_TDM:
209 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
210 setbits_8(&tmp, 0x82);
211 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
212 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
213 clrbits_8(&tmp, 0x82);
214 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
215 break;
216 case MUX_TYPE_CAN:
217 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
218 clrbits_8(&tmp, 0x02);
219 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
220 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
221 clrbits_8(&tmp, 0x02);
222 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
223 break;
224 case MUX_TYPE_CS0_NOR:
225 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
226 clrbits_8(&tmp, 0x08);
227 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
228 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
229 clrbits_8(&tmp, 0x08);
230 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
231 break;
232 case MUX_TYPE_CS0_NAND:
233 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
234 setbits_8(&tmp, 0x08);
235 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
236 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
237 clrbits_8(&tmp, 0x08);
238 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
239 break;
240 default:
241 break;
242 }
243 i2c_set_bus_num(orig_bus);
244#endif
245 return 0;
246}
247
248#ifdef CONFIG_TARGET_P1010RDB_PB
249int i2c_pca9557_read(int type)
250{
251 u8 val;
252
253 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
254 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
255
256 switch (type) {
257 case I2C_READ_BANK:
258 val = (val & 0x10) >> 4;
259 break;
260 case I2C_READ_PCB_VER:
261 val = ((val & 0x60) >> 5) + 1;
262 break;
263 default:
264 break;
265 }
266
267 return val;
268}
269#endif
270
271int checkboard(void)
272{
273 struct cpu_type *cpu;
274 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
275 u8 val;
276
277 cpu = gd->arch.cpu;
278#if defined(CONFIG_TARGET_P1010RDB_PA)
279 printf("Board: %sRDB-PA, ", cpu->name);
280#elif defined(CONFIG_TARGET_P1010RDB_PB)
281 printf("Board: %sRDB-PB, ", cpu->name);
282 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
283 i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
284 val = 0x0;
285 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
286#endif
287
288#ifdef CONFIG_SDCARD
289
290 config_board_mux(MUX_TYPE_IFC);
291#endif
292
293#if defined(CONFIG_TARGET_P1010RDB_PA)
294 val = (in_8(&cpld_data->pcba_ver) & 0xf);
295 printf("PCB: v%x.0\n", val);
296#elif defined(CONFIG_TARGET_P1010RDB_PB)
297 val = in_8(&cpld_data->cpld_ver);
298 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
299 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
300 val = in_8(&cpld_data->rom_loc) & 0xf;
301 puts("Boot from: ");
302 switch (val) {
303 case 0xf:
304 config_board_mux(MUX_TYPE_CS0_NOR);
305 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
306 break;
307 case 0xe:
308 puts("SDHC\n");
309 val = 0x60;
310 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
311 break;
312 case 0x5:
313 config_board_mux(MUX_TYPE_IFC);
314 config_board_mux(MUX_TYPE_CS0_NAND);
315 puts("NAND\n");
316 break;
317 case 0x6:
318 config_board_mux(MUX_TYPE_IFC);
319 puts("SPI\n");
320 break;
321 default:
322 puts("unknown\n");
323 break;
324 }
325#endif
326 return 0;
327}
328
329int board_eth_init(bd_t *bis)
330{
331#ifdef CONFIG_TSEC_ENET
332 struct fsl_pq_mdio_info mdio_info;
333 struct tsec_info_struct tsec_info[4];
334 struct cpu_type *cpu;
335 int num = 0;
336
337 cpu = gd->arch.cpu;
338
339#ifdef CONFIG_TSEC1
340 SET_STD_TSEC_INFO(tsec_info[num], 1);
341 num++;
342#endif
343#ifdef CONFIG_TSEC2
344 SET_STD_TSEC_INFO(tsec_info[num], 2);
345 num++;
346#endif
347#ifdef CONFIG_TSEC3
348
349 if (cpu->soc_ver != SVR_P1014) {
350 SET_STD_TSEC_INFO(tsec_info[num], 3);
351 num++;
352 }
353#endif
354 if (!num) {
355 printf("No TSECs initialized\n");
356 return 0;
357 }
358
359 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
360 mdio_info.name = DEFAULT_MII_NAME;
361
362 fsl_pq_mdio_init(bis, &mdio_info);
363
364 tsec_eth_init(bis, tsec_info, num);
365#endif
366
367 return pci_eth_init(bis);
368}
369
370#if defined(CONFIG_OF_BOARD_SETUP)
371void fdt_del_flexcan(void *blob)
372{
373 int nodeoff = 0;
374
375 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
376 "fsl,p1010-flexcan")) >= 0) {
377 fdt_del_node(blob, nodeoff);
378 }
379}
380
381void fdt_del_spi_flash(void *blob)
382{
383 int nodeoff = 0;
384
385 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
386 "spansion,s25sl12801")) >= 0) {
387 fdt_del_node(blob, nodeoff);
388 }
389}
390
391void fdt_del_spi_slic(void *blob)
392{
393 int nodeoff = 0;
394
395 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
396 "zarlink,le88266")) >= 0) {
397 fdt_del_node(blob, nodeoff);
398 }
399}
400
401void fdt_del_tdm(void *blob)
402{
403 int nodeoff = 0;
404
405 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
406 "fsl,starlite-tdm")) >= 0) {
407 fdt_del_node(blob, nodeoff);
408 }
409}
410
411void fdt_del_sdhc(void *blob)
412{
413 int nodeoff = 0;
414
415 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
416 "fsl,esdhc")) >= 0) {
417 fdt_del_node(blob, nodeoff);
418 }
419}
420
421void fdt_del_ifc(void *blob)
422{
423 int nodeoff = 0;
424
425 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
426 "fsl,ifc")) >= 0) {
427 fdt_del_node(blob, nodeoff);
428 }
429}
430
431void fdt_disable_uart1(void *blob)
432{
433 int nodeoff;
434
435 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
436 CONFIG_SYS_NS16550_COM2);
437
438 if (nodeoff > 0) {
439 fdt_status_disabled(blob, nodeoff);
440 } else {
441 printf("WARNING unable to set status for fsl,ns16550 "
442 "uart1: %s\n", fdt_strerror(nodeoff));
443 }
444}
445
446int ft_board_setup(void *blob, bd_t *bd)
447{
448 phys_addr_t base;
449 phys_size_t size;
450 struct cpu_type *cpu;
451
452 cpu = gd->arch.cpu;
453
454 ft_cpu_setup(blob, bd);
455
456 base = getenv_bootm_low();
457 size = getenv_bootm_size();
458
459#if defined(CONFIG_PCI)
460 FT_FSL_PCI_SETUP;
461#endif
462
463 fdt_fixup_memory(blob, (u64)base, (u64)size);
464
465#if defined(CONFIG_HAS_FSL_DR_USB)
466 fsl_fdt_fixup_dr_usb(blob, bd);
467#endif
468
469
470 if (cpu->soc_ver == SVR_P1014) {
471 fdt_del_flexcan(blob);
472 fdt_del_node_and_alias(blob, "ethernet2");
473 }
474
475
476 if (sd_ifc_mux != MUX_TYPE_IFC)
477 fdt_del_ifc(blob);
478 else
479 fdt_del_sdhc(blob);
480
481 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
482 fdt_del_tdm(blob);
483 fdt_del_spi_slic(blob);
484 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
485 fdt_del_flexcan(blob);
486 fdt_del_spi_flash(blob);
487 fdt_disable_uart1(blob);
488 } else {
489
490
491
492
493
494 fdt_del_tdm(blob);
495 fdt_del_flexcan(blob);
496 fdt_disable_uart1(blob);
497 }
498
499 return 0;
500}
501#endif
502
503#ifdef CONFIG_SDCARD
504int board_mmc_init(bd_t *bis)
505{
506 config_board_mux(MUX_TYPE_SDHC);
507 return -1;
508}
509#else
510void board_reset(void)
511{
512
513 if (sd_ifc_mux != MUX_TYPE_IFC)
514 config_board_mux(MUX_TYPE_IFC);
515}
516#endif
517
518
519int misc_init_r(void)
520{
521 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
522
523 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
524 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
525 MPC85xx_PMUXCR_CAN1_UART |
526 MPC85xx_PMUXCR_CAN2_TDM |
527 MPC85xx_PMUXCR_CAN2_UART);
528 config_board_mux(MUX_TYPE_CAN);
529 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
530 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
531 MPC85xx_PMUXCR_CAN1_UART);
532 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
533 MPC85xx_PMUXCR_CAN1_TDM);
534 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
535 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
536 config_board_mux(MUX_TYPE_TDM);
537 } else {
538
539 config_board_mux(MUX_TYPE_SPIFLASH);
540 }
541
542 if (hwconfig("esdhc"))
543 config_board_mux(MUX_TYPE_SDHC);
544 else if (hwconfig("ifc"))
545 config_board_mux(MUX_TYPE_IFC);
546
547#ifdef CONFIG_TARGET_P1010RDB_PB
548 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
549#endif
550 return 0;
551}
552
553static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
554 char * const argv[])
555{
556 if (argc < 2)
557 return CMD_RET_USAGE;
558 if (strcmp(argv[1], "ifc") == 0)
559 config_board_mux(MUX_TYPE_IFC);
560 else if (strcmp(argv[1], "sdhc") == 0)
561 config_board_mux(MUX_TYPE_SDHC);
562 else
563 return CMD_RET_USAGE;
564 return 0;
565}
566
567U_BOOT_CMD(
568 mux, 2, 0, pin_mux_cmd,
569 "configure multiplexing pin for IFC/SDHC bus in runtime",
570 "bus_type (e.g. mux sdhc)"
571);
572
