LXR uboot/drivers/ddr/marvell/axp/xor.h

   1/*
   2 * Copyright (C) Marvell International Ltd. and its affiliates
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0
   5 */
   6
   7#ifndef __XOR_H
   8#define __XOR_H
   9
  10#include "ddr3_hw_training.h"
  11
  12#define MV_XOR_MAX_CHAN         4 /* total channels for all units together */
  13
  14/*
  15 * This enumerator describes the type of functionality the XOR channel
  16 * can have while using the same data structures.
  17 */
  18enum xor_type {
  19        MV_XOR,         /* XOR channel functions as XOR accelerator     */
  20        MV_DMA,         /* XOR channel functions as IDMA channel        */
  21        MV_CRC32        /* XOR channel functions as CRC 32 calculator   */
  22};
  23
  24/*
  25 * This enumerator describes the set of commands that can be applied on
  26 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
  27 * status (see MV_STATE enumerator)
  28 * Start can be applied only when status is IDLE
  29 * Stop can be applied only when status is IDLE, ACTIVE or PAUSED
  30 * Pause can be applied only when status is ACTIVE
  31 * Restart can be applied only when status is PAUSED
  32 */
  33enum mv_command {
  34        MV_START,               /* Start     */
  35        MV_STOP,                /* Stop     */
  36        MV_PAUSE,               /* Pause    */
  37        MV_RESTART              /* Restart  */
  38};
  39
  40/*
  41 * This enumerator describes the set of state conditions.
  42 * Moving from one state to other is stricted.
  43 */
  44enum mv_state {
  45        MV_IDLE,
  46        MV_ACTIVE,
  47        MV_PAUSED,
  48        MV_UNDEFINED_STATE
  49};
  50
  51/* XOR descriptor structure for CRC and DMA descriptor */
  52struct crc_dma_desc {
  53        u32 status;             /* Successful descriptor execution indication */
  54        u32 crc32_result;       /* Result of CRC-32 calculation */
  55        u32 desc_cmd;           /* type of operation to be carried out on the data */
  56        u32 next_desc_ptr;      /* Next descriptor address pointer */
  57        u32 byte_cnt;           /* Size of source block part represented by the descriptor */
  58        u32 dst_addr;           /* Destination Block address pointer (not used in CRC32 */
  59        u32 src_addr0;          /* Mode: Source Block address pointer */
  60        u32 src_addr1;          /* Mode: Source Block address pointer */
  61} __packed;
  62
  63void mv_xor_hal_init(u32 chan_num);
  64int mv_xor_state_get(u32 chan);
  65void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
  66void mv_sys_xor_finish(void);
  67int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
  68int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
  69                    u32 init_val_low);
  70
  71#endif /* __XOR_H */
  72