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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_FSL_ELBC 1
14
15#define CONFIG_SYS_SRIO
16#define CONFIG_SRIO1
17
18#define CONFIG_PCIE1 1
19#define CONFIG_FSL_PCI_INIT 1
20#define CONFIG_PCI_INDIRECT_BRIDGE 1
21#define CONFIG_FSL_PCIE_RESET 1
22#define CONFIG_SYS_PCI_64BIT 1
23#define CONFIG_QE
24#define CONFIG_ENV_OVERWRITE
25
26#ifndef __ASSEMBLY__
27extern unsigned long get_clock_freq(void);
28#endif
29
30#define CONFIG_SYS_CLK_FREQ 66666666
31#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
32
33#ifdef CONFIG_ATM
34#define CONFIG_PQ_MDS_PIB
35#define CONFIG_PQ_MDS_PIB_ATM
36#endif
37
38
39
40
41#define CONFIG_L2_CACHE
42#define CONFIG_BTB
43
44#ifndef CONFIG_SYS_TEXT_BASE
45#define CONFIG_SYS_TEXT_BASE 0xfff80000
46#endif
47
48#ifndef CONFIG_SYS_MONITOR_BASE
49#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
50#endif
51
52
53
54
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
57#define CONFIG_BOARD_EARLY_INIT_F 1
58#define CONFIG_BOARD_EARLY_INIT_R 1
59#define CONFIG_HWCONFIG
60
61#define CONFIG_SYS_MEMTEST_START 0x00200000
62#define CONFIG_SYS_MEMTEST_END 0x00400000
63
64
65
66
67#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
68#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
69#define CONFIG_SYS_L2_SIZE (512 << 10)
70#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
71
72#define CONFIG_SYS_CCSRBAR 0xe0000000
73#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
74
75#if defined(CONFIG_NAND_SPL)
76#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
77#endif
78
79
80#undef CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SPD_EEPROM
82#define CONFIG_DDR_SPD
83#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
84
85#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86
87#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
88
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
90
91#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
93
94
95#define SPD_EEPROM_ADDRESS 0x51
96
97
98#define CONFIG_SYS_SDRAM_SIZE 1024
99#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
100#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
101#define CONFIG_SYS_DDR_TIMING_3 0x00020000
102#define CONFIG_SYS_DDR_TIMING_0 0x00330004
103#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
104#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
105#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
106#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
107#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
108#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
109#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
110#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
111#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
112#define CONFIG_SYS_DDR_TIMING_4 0x00220001
113#define CONFIG_SYS_DDR_TIMING_5 0x03402400
114#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
115#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
116#define CONFIG_SYS_DDR_CDR_1 0x80040000
117#define CONFIG_SYS_DDR_CDR_2 0x00000000
118#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
119#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
120#define CONFIG_SYS_DDR_CONTROL 0xc7000000
121#define CONFIG_SYS_DDR_CONTROL2 0x24400000
122
123#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
124#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
125#define CONFIG_SYS_DDR_SBE 0x00010000
126
127#undef CONFIG_CLOCKS_IN_MHZ
128
129
130
131
132
133#define CONFIG_SYS_FLASH_BASE 0xfe000000
134#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
135
136#define CONFIG_SYS_BCSR_BASE 0xf8000000
137#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
138
139
140#define CONFIG_FLASH_BR_PRELIM 0xfe000801
141#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
142
143
144#define CONFIG_SYS_BR1_PRELIM 0xf8000801
145#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
146
147
148#define CONFIG_SYS_BR4_PRELIM 0xf8008801
149#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
150
151
152#define CONFIG_SYS_BR5_PRELIM 0xf8010801
153#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
154
155#define CONFIG_SYS_MAX_FLASH_BANKS 1
156#define CONFIG_SYS_MAX_FLASH_SECT 512
157#undef CONFIG_SYS_FLASH_CHECKSUM
158#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
159#define CONFIG_SYS_FLASH_WRITE_TOUT 500
160
161#undef CONFIG_SYS_RAMBOOT
162
163#define CONFIG_FLASH_CFI_DRIVER
164#define CONFIG_SYS_FLASH_CFI
165#define CONFIG_SYS_FLASH_EMPTY_INFO
166
167
168#ifndef CONFIG_NAND_SPL
169#define CONFIG_SYS_NAND_BASE 0xFC000000
170#else
171#define CONFIG_SYS_NAND_BASE 0xFFF00000
172#endif
173
174
175#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
176#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
177#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
178#define CONFIG_SYS_NAND_U_BOOT_START \
179 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
180#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
181#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
182#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
183
184#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
185#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
186#define CONFIG_SYS_MAX_NAND_DEVICE 1
187#define CONFIG_CMD_NAND 1
188#define CONFIG_NAND_FSL_ELBC 1
189#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
190#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
191 | (2<<BR_DECC_SHIFT) \
192 | BR_PS_8 \
193 | BR_MS_FCM \
194 | BR_V)
195#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
196 | OR_FCM_CSCT \
197 | OR_FCM_CST \
198 | OR_FCM_CHT \
199 | OR_FCM_SCY_1 \
200 | OR_FCM_TRLX \
201 | OR_FCM_EHTR)
202
203#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
204#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
205#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM
206#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM
207
208#define CONFIG_SYS_LBC_LCRR 0x00000004
209#define CONFIG_SYS_LBC_LBCR 0x00040000
210#define CONFIG_SYS_LBC_LSRT 0x20000000
211#define CONFIG_SYS_LBC_MRTPR 0x00000000
212
213#define CONFIG_SYS_INIT_RAM_LOCK 1
214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
215#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
216
217#define CONFIG_SYS_GBL_DATA_OFFSET \
218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220
221#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
222#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
223
224
225#define CONFIG_CONS_INDEX 1
226#define CONFIG_SYS_NS16550_SERIAL
227#define CONFIG_SYS_NS16550_REG_SIZE 1
228#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
229#ifdef CONFIG_NAND_SPL
230#define CONFIG_NS16550_MIN_FUNCTIONS
231#endif
232
233#define CONFIG_SYS_BAUDRATE_TABLE \
234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
235
236#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
237#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
238
239
240
241
242#define CONFIG_SYS_I2C
243#define CONFIG_SYS_I2C_FSL
244#define CONFIG_SYS_FSL_I2C_SPEED 400000
245#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
246#define CONFIG_SYS_FSL_I2C2_SPEED 400000
247#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
248#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
249#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
250#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
251
252
253
254
255#define CONFIG_ID_EEPROM
256#ifdef CONFIG_ID_EEPROM
257#define CONFIG_SYS_I2C_EEPROM_NXID
258#endif
259#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
260#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
261#define CONFIG_SYS_EEPROM_BUS_NUM 1
262
263#define PLPPAR1_I2C_BIT_MASK 0x0000000F
264#define PLPPAR1_I2C2_VAL 0x00000000
265#define PLPPAR1_ESDHC_VAL 0x0000000A
266#define PLPDIR1_I2C_BIT_MASK 0x0000000F
267#define PLPDIR1_I2C2_VAL 0x0000000F
268#define PLPDIR1_ESDHC_VAL 0x00000006
269#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
270#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
271#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
272#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
273
274
275
276
277
278#define CONFIG_SYS_PCIE1_NAME "Slot"
279#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
280#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
281#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
282#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
283#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
284#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
285#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
286#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
287
288#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
289#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
290#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
291#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
292
293#ifdef CONFIG_QE
294
295
296
297#define CONFIG_SYS_UCC_RGMII_MODE
298#undef CONFIG_SYS_UCC_RMII_MODE
299
300#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
301#define CONFIG_UEC_ETH
302#define CONFIG_ETHPRIME "UEC0"
303#define CONFIG_PHY_MODE_NEED_CHANGE
304
305#define CONFIG_UEC_ETH1
306#define CONFIG_HAS_ETH0
307
308#ifdef CONFIG_UEC_ETH1
309#define CONFIG_SYS_UEC1_UCC_NUM 0
310#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
311#if defined(CONFIG_SYS_UCC_RGMII_MODE)
312#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
313#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
314#define CONFIG_SYS_UEC1_PHY_ADDR 7
315#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
316#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
317#elif defined(CONFIG_SYS_UCC_RMII_MODE)
318#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
319#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
320#define CONFIG_SYS_UEC1_PHY_ADDR 8
321#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
322#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
323#endif
324#endif
325
326#define CONFIG_UEC_ETH2
327#define CONFIG_HAS_ETH1
328
329#ifdef CONFIG_UEC_ETH2
330#define CONFIG_SYS_UEC2_UCC_NUM 1
331#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
332#if defined(CONFIG_SYS_UCC_RGMII_MODE)
333#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
334#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
335#define CONFIG_SYS_UEC2_PHY_ADDR 1
336#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
337#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
338#elif defined(CONFIG_SYS_UCC_RMII_MODE)
339#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
340#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
341#define CONFIG_SYS_UEC2_PHY_ADDR 0x9
342#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
343#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
344#endif
345#endif
346
347#define CONFIG_UEC_ETH3
348#define CONFIG_HAS_ETH2
349
350#ifdef CONFIG_UEC_ETH3
351#define CONFIG_SYS_UEC3_UCC_NUM 2
352#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
353#if defined(CONFIG_SYS_UCC_RGMII_MODE)
354#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
355#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
356#define CONFIG_SYS_UEC3_PHY_ADDR 2
357#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
358#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
359#elif defined(CONFIG_SYS_UCC_RMII_MODE)
360#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16
361#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
362#define CONFIG_SYS_UEC3_PHY_ADDR 0xA
363#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
364#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
365#endif
366#endif
367
368#define CONFIG_UEC_ETH4
369#define CONFIG_HAS_ETH3
370
371#ifdef CONFIG_UEC_ETH4
372#define CONFIG_SYS_UEC4_UCC_NUM 3
373#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
374#if defined(CONFIG_SYS_UCC_RGMII_MODE)
375#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
376#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
377#define CONFIG_SYS_UEC4_PHY_ADDR 3
378#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
379#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
380#elif defined(CONFIG_SYS_UCC_RMII_MODE)
381#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16
382#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
383#define CONFIG_SYS_UEC4_PHY_ADDR 0xB
384#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
385#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
386#endif
387#endif
388
389#undef CONFIG_UEC_ETH6
390#define CONFIG_HAS_ETH5
391
392#ifdef CONFIG_UEC_ETH6
393#define CONFIG_SYS_UEC6_UCC_NUM 5
394#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
395#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
396#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
397#define CONFIG_SYS_UEC6_PHY_ADDR 4
398#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
399#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
400#endif
401
402#undef CONFIG_UEC_ETH8
403#define CONFIG_HAS_ETH7
404
405#ifdef CONFIG_UEC_ETH8
406#define CONFIG_SYS_UEC8_UCC_NUM 7
407#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
408#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
409#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
410#define CONFIG_SYS_UEC8_PHY_ADDR 6
411#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
412#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
413#endif
414
415#endif
416
417#if defined(CONFIG_PCI)
418#undef CONFIG_EEPRO100
419#undef CONFIG_TULIP
420
421#undef CONFIG_PCI_SCAN_SHOW
422
423#endif
424
425
426
427
428#if defined(CONFIG_SYS_RAMBOOT)
429#else
430#define CONFIG_ENV_IS_IN_FLASH 1
431#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
432#define CONFIG_ENV_SECT_SIZE 0x20000
433#define CONFIG_ENV_SIZE 0x2000
434#endif
435
436#define CONFIG_LOADS_ECHO 1
437#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
438
439
440#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
441#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
442
443
444
445
446#define CONFIG_BOOTP_BOOTFILESIZE
447#define CONFIG_BOOTP_BOOTPATH
448#define CONFIG_BOOTP_GATEWAY
449#define CONFIG_BOOTP_HOSTNAME
450
451
452
453
454#define CONFIG_CMD_IRQ
455#define CONFIG_CMD_REGINFO
456
457#if defined(CONFIG_PCI)
458 #define CONFIG_CMD_PCI
459#endif
460
461#undef CONFIG_WATCHDOG
462
463#ifdef CONFIG_MMC
464#define CONFIG_FSL_ESDHC
465#define CONFIG_FSL_ESDHC_PIN_MUX
466#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
467#define CONFIG_GENERIC_MMC
468#define CONFIG_DOS_PARTITION
469#endif
470
471
472
473
474#define CONFIG_SYS_LONGHELP
475#define CONFIG_CMDLINE_EDITING
476#define CONFIG_AUTO_COMPLETE
477#define CONFIG_SYS_LOAD_ADDR 0x2000000
478#if defined(CONFIG_CMD_KGDB)
479#define CONFIG_SYS_CBSIZE 2048
480#else
481#define CONFIG_SYS_CBSIZE 512
482#endif
483#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
484
485#define CONFIG_SYS_MAXARGS 32
486#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
487
488
489
490
491
492
493
494#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
495#define CONFIG_SYS_BOOTM_LEN (64 << 20)
496
497#if defined(CONFIG_CMD_KGDB)
498#define CONFIG_KGDB_BAUDRATE 230400
499#endif
500
501
502
503
504#define CONFIG_HOSTNAME mpc8569mds
505#define CONFIG_ROOTPATH "/nfsroot"
506#define CONFIG_BOOTFILE "your.uImage"
507
508#define CONFIG_SERVERIP 192.168.1.1
509#define CONFIG_GATEWAYIP 192.168.1.1
510#define CONFIG_NETMASK 255.255.255.0
511
512#define CONFIG_LOADADDR 200000
513
514#undef CONFIG_BOOTARGS
515
516#define CONFIG_BAUDRATE 115200
517
518#define CONFIG_EXTRA_ENV_SETTINGS \
519 "netdev=eth0\0" \
520 "consoledev=ttyS0\0" \
521 "ramdiskaddr=600000\0" \
522 "ramdiskfile=your.ramdisk.u-boot\0" \
523 "fdtaddr=400000\0" \
524 "fdtfile=your.fdt.dtb\0" \
525 "nfsargs=setenv bootargs root=/dev/nfs rw " \
526 "nfsroot=$serverip:$rootpath " \
527 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
528 "console=$consoledev,$baudrate $othbootargs\0" \
529 "ramargs=setenv bootargs root=/dev/ram rw " \
530 "console=$consoledev,$baudrate $othbootargs\0" \
531
532#define CONFIG_NFSBOOTCOMMAND \
533 "run nfsargs;" \
534 "tftp $loadaddr $bootfile;" \
535 "tftp $fdtaddr $fdtfile;" \
536 "bootm $loadaddr - $fdtaddr"
537
538#define CONFIG_RAMBOOTCOMMAND \
539 "run ramargs;" \
540 "tftp $ramdiskaddr $ramdiskfile;" \
541 "tftp $loadaddr $bootfile;" \
542 "bootm $loadaddr $ramdiskaddr"
543
544#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
545
546#endif
547