LXR uboot/include/tsec.h

   1/*
   2 *  tsec.h
   3 *
   4 *  Driver for the Motorola Triple Speed Ethernet Controller
   5 *
   6 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
   7 * (C) Copyright 2003, Motorola, Inc.
   8 * maintained by Xianghua Xiao (x.xiao@motorola.com)
   9 * author Andy Fleming
  10 *
  11 * SPDX-License-Identifier:     GPL-2.0+
  12 */
  13
  14#ifndef __TSEC_H
  15#define __TSEC_H
  16
  17#include <net.h>
  18#include <config.h>
  19#include <phy.h>
  20
  21#ifndef CONFIG_DM_ETH
  22
  23#ifdef CONFIG_LS102XA
  24#define TSEC_SIZE               0x40000
  25#define TSEC_MDIO_OFFSET        0x40000
  26#else
  27#define TSEC_SIZE               0x01000
  28#define TSEC_MDIO_OFFSET        0x01000
  29#endif
  30
  31#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
  32
  33#define TSEC_GET_REGS(num, offset) \
  34        (struct tsec __iomem *)\
  35        (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
  36
  37#define TSEC_GET_REGS_BASE(num) \
  38        TSEC_GET_REGS((num), TSEC_SIZE)
  39
  40#define TSEC_GET_MDIO_REGS(num, offset) \
  41        (struct tsec_mii_mng __iomem *)\
  42        (CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
  43
  44#define TSEC_GET_MDIO_REGS_BASE(num) \
  45        TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
  46
  47#define DEFAULT_MII_NAME "FSL_MDIO"
  48
  49#define STD_TSEC_INFO(num) \
  50{                       \
  51        .regs = TSEC_GET_REGS_BASE(num), \
  52        .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
  53        .devname = CONFIG_TSEC##num##_NAME, \
  54        .phyaddr = TSEC##num##_PHY_ADDR, \
  55        .flags = TSEC##num##_FLAGS, \
  56        .mii_devname = DEFAULT_MII_NAME \
  57}
  58
  59#define SET_STD_TSEC_INFO(x, num) \
  60{                       \
  61        x.regs = TSEC_GET_REGS_BASE(num); \
  62        x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
  63        x.devname = CONFIG_TSEC##num##_NAME; \
  64        x.phyaddr = TSEC##num##_PHY_ADDR; \
  65        x.flags = TSEC##num##_FLAGS;\
  66        x.mii_devname = DEFAULT_MII_NAME;\
  67}
  68
  69#endif /* CONFIG_DM_ETH */
  70
  71#define MAC_ADDR_LEN            6
  72
  73/* #define TSEC_TIMEOUT 1000000 */
  74#define TSEC_TIMEOUT            1000
  75#define TOUT_LOOP               1000000
  76
  77/* TBI register addresses */
  78#define TBI_CR                  0x00
  79#define TBI_SR                  0x01
  80#define TBI_ANA                 0x04
  81#define TBI_ANLPBPA             0x05
  82#define TBI_ANEX                0x06
  83#define TBI_TBICON              0x11
  84
  85/* TBI MDIO register bit fields*/
  86#define TBICON_CLK_SELECT       0x0020
  87#define TBIANA_ASYMMETRIC_PAUSE 0x0100
  88#define TBIANA_SYMMETRIC_PAUSE  0x0080
  89#define TBIANA_HALF_DUPLEX      0x0040
  90#define TBIANA_FULL_DUPLEX      0x0020
  91#define TBICR_PHY_RESET         0x8000
  92#define TBICR_ANEG_ENABLE       0x1000
  93#define TBICR_RESTART_ANEG      0x0200
  94#define TBICR_FULL_DUPLEX       0x0100
  95#define TBICR_SPEED1_SET        0x0040
  96
  97/* MAC register bits */
  98#define MACCFG1_SOFT_RESET      0x80000000
  99#define MACCFG1_RESET_RX_MC     0x00080000
 100#define MACCFG1_RESET_TX_MC     0x00040000
 101#define MACCFG1_RESET_RX_FUN    0x00020000
 102#define MACCFG1_RESET_TX_FUN    0x00010000
 103#define MACCFG1_LOOPBACK        0x00000100
 104#define MACCFG1_RX_FLOW         0x00000020
 105#define MACCFG1_TX_FLOW         0x00000010
 106#define MACCFG1_SYNCD_RX_EN     0x00000008
 107#define MACCFG1_RX_EN           0x00000004
 108#define MACCFG1_SYNCD_TX_EN     0x00000002
 109#define MACCFG1_TX_EN           0x00000001
 110
 111#define MACCFG2_INIT_SETTINGS   0x00007205
 112#define MACCFG2_FULL_DUPLEX     0x00000001
 113#define MACCFG2_IF              0x00000300
 114#define MACCFG2_GMII            0x00000200
 115#define MACCFG2_MII             0x00000100
 116
 117#define ECNTRL_INIT_SETTINGS    0x00001000
 118#define ECNTRL_TBI_MODE         0x00000020
 119#define ECNTRL_REDUCED_MODE     0x00000010
 120#define ECNTRL_R100             0x00000008
 121#define ECNTRL_REDUCED_MII_MODE 0x00000004
 122#define ECNTRL_SGMII_MODE       0x00000002
 123
 124#ifndef CONFIG_SYS_TBIPA_VALUE
 125# define CONFIG_SYS_TBIPA_VALUE 0x1f
 126#endif
 127
 128#define MRBLR_INIT_SETTINGS     PKTSIZE_ALIGN
 129
 130#define MINFLR_INIT_SETTINGS    0x00000040
 131
 132#define DMACTRL_INIT_SETTINGS   0x000000c3
 133#define DMACTRL_GRS             0x00000010
 134#define DMACTRL_GTS             0x00000008
 135#define DMACTRL_LE              0x00008000
 136
 137#define TSTAT_CLEAR_THALT       0x80000000
 138#define RSTAT_CLEAR_RHALT       0x00800000
 139
 140#define IEVENT_INIT_CLEAR       0xffffffff
 141#define IEVENT_BABR             0x80000000
 142#define IEVENT_RXC              0x40000000
 143#define IEVENT_BSY              0x20000000
 144#define IEVENT_EBERR            0x10000000
 145#define IEVENT_MSRO             0x04000000
 146#define IEVENT_GTSC             0x02000000
 147#define IEVENT_BABT             0x01000000
 148#define IEVENT_TXC              0x00800000
 149#define IEVENT_TXE              0x00400000
 150#define IEVENT_TXB              0x00200000
 151#define IEVENT_TXF              0x00100000
 152#define IEVENT_IE               0x00080000
 153#define IEVENT_LC               0x00040000
 154#define IEVENT_CRL              0x00020000
 155#define IEVENT_XFUN             0x00010000
 156#define IEVENT_RXB0             0x00008000
 157#define IEVENT_GRSC             0x00000100
 158#define IEVENT_RXF0             0x00000080
 159
 160#define IMASK_INIT_CLEAR        0x00000000
 161#define IMASK_TXEEN             0x00400000
 162#define IMASK_TXBEN             0x00200000
 163#define IMASK_TXFEN             0x00100000
 164#define IMASK_RXFEN0            0x00000080
 165
 166/* Default Attribute fields */
 167#define ATTR_INIT_SETTINGS      0x000000c0
 168#define ATTRELI_INIT_SETTINGS   0x00000000
 169
 170/* TxBD status field bits */
 171#define TXBD_READY              0x8000
 172#define TXBD_PADCRC             0x4000
 173#define TXBD_WRAP               0x2000
 174#define TXBD_INTERRUPT          0x1000
 175#define TXBD_LAST               0x0800
 176#define TXBD_CRC                0x0400
 177#define TXBD_DEF                0x0200
 178#define TXBD_HUGEFRAME          0x0080
 179#define TXBD_LATECOLLISION      0x0080
 180#define TXBD_RETRYLIMIT         0x0040
 181#define TXBD_RETRYCOUNTMASK     0x003c
 182#define TXBD_UNDERRUN           0x0002
 183#define TXBD_STATS              0x03ff
 184
 185/* RxBD status field bits */
 186#define RXBD_EMPTY              0x8000
 187#define RXBD_RO1                0x4000
 188#define RXBD_WRAP               0x2000
 189#define RXBD_INTERRUPT          0x1000
 190#define RXBD_LAST               0x0800
 191#define RXBD_FIRST              0x0400
 192#define RXBD_MISS               0x0100
 193#define RXBD_BROADCAST          0x0080
 194#define RXBD_MULTICAST          0x0040
 195#define RXBD_LARGE              0x0020
 196#define RXBD_NONOCTET           0x0010
 197#define RXBD_SHORT              0x0008
 198#define RXBD_CRCERR             0x0004
 199#define RXBD_OVERRUN            0x0002
 200#define RXBD_TRUNCATED          0x0001
 201#define RXBD_STATS              0x003f
 202
 203struct txbd8 {
 204        uint16_t status;        /* Status Fields */
 205        uint16_t length;        /* Buffer length */
 206        uint32_t bufptr;        /* Buffer Pointer */
 207};
 208
 209struct rxbd8 {
 210        uint16_t status;        /* Status Fields */
 211        uint16_t length;        /* Buffer Length */
 212        uint32_t bufptr;        /* Buffer Pointer */
 213};
 214
 215struct tsec_rmon_mib {
 216        /* Transmit and Receive Counters */
 217        u32     tr64;           /* Tx/Rx 64-byte Frame Counter */
 218        u32     tr127;          /* Tx/Rx 65-127 byte Frame Counter */
 219        u32     tr255;          /* Tx/Rx 128-255 byte Frame Counter */
 220        u32     tr511;          /* Tx/Rx 256-511 byte Frame Counter */
 221        u32     tr1k;           /* Tx/Rx 512-1023 byte Frame Counter */
 222        u32     trmax;          /* Tx/Rx 1024-1518 byte Frame Counter */
 223        u32     trmgv;          /* Tx/Rx 1519-1522 byte Good VLAN Frame */
 224        /* Receive Counters */
 225        u32     rbyt;           /* Receive Byte Counter */
 226        u32     rpkt;           /* Receive Packet Counter */
 227        u32     rfcs;           /* Receive FCS Error Counter */
 228        u32     rmca;           /* Receive Multicast Packet (Counter) */
 229        u32     rbca;           /* Receive Broadcast Packet */
 230        u32     rxcf;           /* Receive Control Frame Packet */
 231        u32     rxpf;           /* Receive Pause Frame Packet */
 232        u32     rxuo;           /* Receive Unknown OP Code */
 233        u32     raln;           /* Receive Alignment Error */
 234        u32     rflr;           /* Receive Frame Length Error */
 235        u32     rcde;           /* Receive Code Error */
 236        u32     rcse;           /* Receive Carrier Sense Error */
 237        u32     rund;           /* Receive Undersize Packet */
 238        u32     rovr;           /* Receive Oversize Packet */
 239        u32     rfrg;           /* Receive Fragments */
 240        u32     rjbr;           /* Receive Jabber */
 241        u32     rdrp;           /* Receive Drop */
 242        /* Transmit Counters */
 243        u32     tbyt;           /* Transmit Byte Counter */
 244        u32     tpkt;           /* Transmit Packet */
 245        u32     tmca;           /* Transmit Multicast Packet */
 246        u32     tbca;           /* Transmit Broadcast Packet */
 247        u32     txpf;           /* Transmit Pause Control Frame */
 248        u32     tdfr;           /* Transmit Deferral Packet */
 249        u32     tedf;           /* Transmit Excessive Deferral Packet */
 250        u32     tscl;           /* Transmit Single Collision Packet */
 251        /* (0x2_n700) */
 252        u32     tmcl;           /* Transmit Multiple Collision Packet */
 253        u32     tlcl;           /* Transmit Late Collision Packet */
 254        u32     txcl;           /* Transmit Excessive Collision Packet */
 255        u32     tncl;           /* Transmit Total Collision */
 256
 257        u32     res2;
 258
 259        u32     tdrp;           /* Transmit Drop Frame */
 260        u32     tjbr;           /* Transmit Jabber Frame */
 261        u32     tfcs;           /* Transmit FCS Error */
 262        u32     txcf;           /* Transmit Control Frame */
 263        u32     tovr;           /* Transmit Oversize Frame */
 264        u32     tund;           /* Transmit Undersize Frame */
 265        u32     tfrg;           /* Transmit Fragments Frame */
 266        /* General Registers */
 267        u32     car1;           /* Carry Register One */
 268        u32     car2;           /* Carry Register Two */
 269        u32     cam1;           /* Carry Register One Mask */
 270        u32     cam2;           /* Carry Register Two Mask */
 271};
 272
 273struct tsec_hash_regs {
 274        u32     iaddr0;         /* Individual Address Register 0 */
 275        u32     iaddr1;         /* Individual Address Register 1 */
 276        u32     iaddr2;         /* Individual Address Register 2 */
 277        u32     iaddr3;         /* Individual Address Register 3 */
 278        u32     iaddr4;         /* Individual Address Register 4 */
 279        u32     iaddr5;         /* Individual Address Register 5 */
 280        u32     iaddr6;         /* Individual Address Register 6 */
 281        u32     iaddr7;         /* Individual Address Register 7 */
 282        u32     res1[24];
 283        u32     gaddr0;         /* Group Address Register 0 */
 284        u32     gaddr1;         /* Group Address Register 1 */
 285        u32     gaddr2;         /* Group Address Register 2 */
 286        u32     gaddr3;         /* Group Address Register 3 */
 287        u32     gaddr4;         /* Group Address Register 4 */
 288        u32     gaddr5;         /* Group Address Register 5 */
 289        u32     gaddr6;         /* Group Address Register 6 */
 290        u32     gaddr7;         /* Group Address Register 7 */
 291        u32     res2[24];
 292};
 293
 294struct tsec {
 295        /* General Control and Status Registers (0x2_n000) */
 296        u32     res000[4];
 297
 298        u32     ievent;         /* Interrupt Event */
 299        u32     imask;          /* Interrupt Mask */
 300        u32     edis;           /* Error Disabled */
 301        u32     res01c;
 302        u32     ecntrl;         /* Ethernet Control */
 303        u32     minflr;         /* Minimum Frame Length */
 304        u32     ptv;            /* Pause Time Value */
 305        u32     dmactrl;        /* DMA Control */
 306        u32     tbipa;          /* TBI PHY Address */
 307
 308        u32     res034[3];
 309        u32     res040[48];
 310
 311        /* Transmit Control and Status Registers (0x2_n100) */
 312        u32     tctrl;          /* Transmit Control */
 313        u32     tstat;          /* Transmit Status */
 314        u32     res108;
 315        u32     tbdlen;         /* Tx BD Data Length */
 316        u32     res110[5];
 317        u32     ctbptr;         /* Current TxBD Pointer */
 318        u32     res128[23];
 319        u32     tbptr;          /* TxBD Pointer */
 320        u32     res188[30];
 321        /* (0x2_n200) */
 322        u32     res200;
 323        u32     tbase;          /* TxBD Base Address */
 324        u32     res208[42];
 325        u32     ostbd;          /* Out of Sequence TxBD */
 326        u32     ostbdp;         /* Out of Sequence Tx Data Buffer Pointer */
 327        u32     res2b8[18];
 328
 329        /* Receive Control and Status Registers (0x2_n300) */
 330        u32     rctrl;          /* Receive Control */
 331        u32     rstat;          /* Receive Status */
 332        u32     res308;
 333        u32     rbdlen;         /* RxBD Data Length */
 334        u32     res310[4];
 335        u32     res320;
 336        u32     crbptr;         /* Current Receive Buffer Pointer */
 337        u32     res328[6];
 338        u32     mrblr;          /* Maximum Receive Buffer Length */
 339        u32     res344[16];
 340        u32     rbptr;          /* RxBD Pointer */
 341        u32     res388[30];
 342        /* (0x2_n400) */
 343        u32     res400;
 344        u32     rbase;          /* RxBD Base Address */
 345        u32     res408[62];
 346
 347        /* MAC Registers (0x2_n500) */
 348        u32     maccfg1;        /* MAC Configuration #1 */
 349        u32     maccfg2;        /* MAC Configuration #2 */
 350        u32     ipgifg;         /* Inter Packet Gap/Inter Frame Gap */
 351        u32     hafdup;         /* Half-duplex */
 352        u32     maxfrm;         /* Maximum Frame */
 353        u32     res514;
 354        u32     res518;
 355
 356        u32     res51c;
 357
 358        u32     resmdio[6];
 359
 360        u32     res538;
 361
 362        u32     ifstat;         /* Interface Status */
 363        u32     macstnaddr1;    /* Station Address, part 1 */
 364        u32     macstnaddr2;    /* Station Address, part 2 */
 365        u32     res548[46];
 366
 367        /* (0x2_n600) */
 368        u32     res600[32];
 369
 370        /* RMON MIB Registers (0x2_n680-0x2_n73c) */
 371        struct tsec_rmon_mib    rmon;
 372        u32     res740[48];
 373
 374        /* Hash Function Registers (0x2_n800) */
 375        struct tsec_hash_regs   hash;
 376
 377        u32     res900[128];
 378
 379        /* Pattern Registers (0x2_nb00) */
 380        u32     resb00[62];
 381        u32     attr; /* Default Attribute Register */
 382        u32     attreli; /* Default Attribute Extract Length and Index */
 383
 384        /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
 385        u32     resc00[256];
 386};
 387
 388#define TSEC_GIGABIT    (1 << 0)
 389
 390/* These flags currently only have meaning if we're using the eTSEC */
 391#define TSEC_REDUCED    (1 << 1)        /* MAC-PHY interface uses RGMII */
 392#define TSEC_SGMII      (1 << 2)        /* MAC-PHY interface uses SGMII */
 393
 394#define TX_BUF_CNT      2
 395
 396struct tsec_private {
 397        struct txbd8 __iomem txbd[TX_BUF_CNT];
 398        struct rxbd8 __iomem rxbd[PKTBUFSRX];
 399        struct tsec __iomem *regs;
 400        struct tsec_mii_mng __iomem *phyregs_sgmii;
 401        struct phy_device *phydev;
 402        phy_interface_t interface;
 403        struct mii_dev *bus;
 404        uint phyaddr;
 405        uint tbiaddr;
 406        char mii_devname[16];
 407        u32 flags;
 408        uint rx_idx;    /* index of the current RX buffer */
 409        uint tx_idx;    /* index of the current TX buffer */
 410#ifndef CONFIG_DM_ETH
 411        struct eth_device *dev;
 412#else
 413        struct udevice *dev;
 414#endif
 415};
 416
 417struct tsec_info_struct {
 418        struct tsec __iomem *regs;
 419        struct tsec_mii_mng __iomem *miiregs_sgmii;
 420        char *devname;
 421        char *mii_devname;
 422        phy_interface_t interface;
 423        unsigned int phyaddr;
 424        u32 flags;
 425};
 426
 427#ifndef CONFIG_DM_ETH
 428int tsec_standard_init(bd_t *bis);
 429int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
 430#endif
 431
 432#endif /* __TSEC_H */
 433