LXR uboot/include/usb/fusbh200.h

   1/*
   2 * Faraday USB 2.0 EHCI Controller
   3 *
   4 * (C) Copyright 2010 Faraday Technology
   5 * Dante Su <dantesu@faraday-tech.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#ifndef _FUSBH200_H
  11#define _FUSBH200_H
  12
  13struct fusbh200_regs {
  14        struct {
  15                uint32_t data[4];
  16        } hccr;                 /* 0x00 - 0x0f: hccr */
  17        struct {
  18                uint32_t data[9];
  19        } hcor;                 /* 0x10 - 0x33: hcor */
  20        uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */
  21        uint32_t rsvd[2];
  22        uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */
  23        uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */
  24        uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
  25};
  26
  27/* EOF & Async. Schedule Sleep Timer Register */
  28#define EASSTR_RUNNING  (1 << 6) /* Put transceiver in running/resume mode */
  29#define EASSTR_SUSPEND  (0 << 6) /* Put transceiver in suspend mode */
  30#define EASSTR_EOF2(x)  (((x) & 0x3) << 4) /* EOF 2 Timing */
  31#define EASSTR_EOF1(x)  (((x) & 0x3) << 2) /* EOF 1 Timing */
  32#define EASSTR_ASST(x)  (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
  33
  34/* Bus Monitor Control Status Register */
  35#define BMCSR_SPD_HIGH  (2 << 9) /* Speed of the attached device */
  36#define BMCSR_SPD_LOW   (1 << 9)
  37#define BMCSR_SPD_FULL  (0 << 9)
  38#define BMCSR_SPD_MASK  (3 << 9)
  39#define BMCSR_SPD_SHIFT 9
  40#define BMCSR_SPD(x)    ((x >> 9) & 0x03)
  41#define BMCSR_VBUS      (1 << 8) /* VBUS Valid */
  42#define BMCSR_VBUS_OFF  (1 << 4) /* VBUS Off */
  43#define BMCSR_VBUS_ON   (0 << 4) /* VBUS On */
  44#define BMCSR_IRQLH     (1 << 3) /* IRQ triggered at level-high */
  45#define BMCSR_IRQLL     (0 << 3) /* IRQ triggered at level-low */
  46#define BMCSR_HALFSPD   (1 << 2) /* Half speed mode for FPGA test */
  47#define BMCSR_HFT_LONG  (1 << 1) /* HDISCON noise filter = 270 us*/
  48#define BMCSR_HFT       (0 << 1) /* HDISCON noise filter = 135 us*/
  49#define BMCSR_VFT_LONG  (1 << 1) /* VBUS noise filter = 472 us*/
  50#define BMCSR_VFT       (0 << 1) /* VBUS noise filter = 135 us*/
  51
  52/* Bus Monitor Interrupt Status Register */
  53/* Bus Monitor Interrupt Enable Register */
  54#define BMISR_DMAERR    (1 << 4) /* DMA error */
  55#define BMISR_DMA       (1 << 3) /* DMA complete */
  56#define BMISR_DEVRM     (1 << 2) /* device removed */
  57#define BMISR_OVD       (1 << 1) /* over-current detected */
  58#define BMISR_VBUSERR   (1 << 0) /* VBUS error */
  59
  60#endif
  61