1/* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 8#define __ARCH_FSL_LSCH2_IMMAP_H__ 9 10#include <fsl_immap.h> 11 12#define CONFIG_SYS_IMMR 0x01000000 13#define CONFIG_SYS_DCSRBAR 0x20000000 14#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 15#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 16 17#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 19#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 20#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 21#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 22#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 23#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 24#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 25#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 26#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 27#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 28#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 29#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 30#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 31#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 32#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 33#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 34#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 35#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 36#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 37#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 38#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 39#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 40#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 41#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 42#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 43 44#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 45 46#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 47#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 48#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 49#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 50 51#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 52 53#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 54#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 55 56#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 57 58#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 59 60#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 61#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 62#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 63/* LUT registers */ 64#ifdef CONFIG_ARCH_LS1012A 65#define PCIE_LUT_BASE 0xC0000 66#else 67#define PCIE_LUT_BASE 0x10000 68#endif 69#define PCIE_LUT_LCTRL0 0x7F8 70#define PCIE_LUT_DBG 0x7FC 71 72/* TZ Address Space Controller Definitions */ 73#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 74#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 75#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 76#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 77#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 78#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 79#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 80#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 81#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 82#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 83#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 84#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 85#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 86 87#define TP_ITYP_AV 0x00000001 /* Initiator available */ 88#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 89#define TP_ITYP_TYPE_ARM 0x0 90#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 91#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 92#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 93#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 94#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 95#define TY_ITYP_VER_A7 0x1 96#define TY_ITYP_VER_A53 0x2 97#define TY_ITYP_VER_A57 0x3 98#define TY_ITYP_VER_A72 0x4 99 100#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 101#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 102#define TP_INIT_PER_CLUSTER 4 103 104/* 105 * Define default values for some CCSR macros to make header files cleaner* 106 * 107 * To completely disable CCSR relocation in a board header file, define 108 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 109 * to a value that is the same as CONFIG_SYS_CCSRBAR. 110 */ 111 112#ifdef CONFIG_SYS_CCSRBAR_PHYS 113#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 114CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 115#endif 116 117#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 118#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 119#undef CONFIG_SYS_CCSRBAR_PHYS_LOW 120#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 121#endif 122 123#ifndef CONFIG_SYS_CCSRBAR 124#define CONFIG_SYS_CCSRBAR 0x01000000 125#endif 126 127#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 128#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 129#endif 130 131#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 132#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 133#endif 134 135#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 136 CONFIG_SYS_CCSRBAR_PHYS_LOW) 137 138struct sys_info { 139 unsigned long freq_processor[CONFIG_MAX_CPUS]; 140 /* frequency of platform PLL */ 141 unsigned long freq_systembus; 142 unsigned long freq_ddrbus; 143 unsigned long freq_localbus; 144 unsigned long freq_sdhc; 145#ifdef CONFIG_SYS_DPAA_FMAN 146 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 147#endif 148 unsigned long freq_qman; 149}; 150 151#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 152#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 153#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 154#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 155#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 156#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 157#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 158 159#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 160#define CONFIG_SYS_FSL_FM1_ADDR \ 161 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 162#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 163 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 164 165#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 166#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 167#define CONFIG_SYS_FSL_SEC_ADDR \ 168 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 169#define CONFIG_SYS_FSL_JR0_ADDR \ 170 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 171 172/* Device Configuration and Pin Control */ 173#define DCFG_DCSR_PORCR1 0x0 174 175struct ccsr_gur { 176 u32 porsr1; /* POR status 1 */ 177#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 178 u32 porsr2; /* POR status 2 */ 179 u8 res_008[0x20-0x8]; 180 u32 gpporcr1; /* General-purpose POR configuration */ 181 u32 gpporcr2; 182#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 183#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 184#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 185#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 186 u32 dcfg_fusesr; /* Fuse status register */ 187 u8 res_02c[0x70-0x2c]; 188 u32 devdisr; /* Device disable control */ 189#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 190#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 191#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 192#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 193#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 194#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 195#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 196#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 197#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 198#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 199#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 200#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 201 u32 devdisr2; /* Device disable control 2 */ 202 u32 devdisr3; /* Device disable control 3 */ 203 u32 devdisr4; /* Device disable control 4 */ 204 u32 devdisr5; /* Device disable control 5 */ 205 u32 devdisr6; /* Device disable control 6 */ 206 u32 devdisr7; /* Device disable control 7 */ 207 u8 res_08c[0x94-0x8c]; 208 u32 coredisru; /* uppper portion for support of 64 cores */ 209 u32 coredisrl; /* lower portion for support of 64 cores */ 210 u8 res_09c[0xa0-0x9c]; 211 u32 pvr; /* Processor version */ 212 u32 svr; /* System version */ 213 u32 mvr; /* Manufacturing version */ 214 u8 res_0ac[0xb0-0xac]; 215 u32 rstcr; /* Reset control */ 216 u32 rstrqpblsr; /* Reset request preboot loader status */ 217 u8 res_0b8[0xc0-0xb8]; 218 u32 rstrqmr1; /* Reset request mask */ 219 u8 res_0c4[0xc8-0xc4]; 220 u32 rstrqsr1; /* Reset request status */ 221 u8 res_0cc[0xd4-0xcc]; 222 u32 rstrqwdtmrl; /* Reset request WDT mask */ 223 u8 res_0d8[0xdc-0xd8]; 224 u32 rstrqwdtsrl; /* Reset request WDT status */ 225 u8 res_0e0[0xe4-0xe0]; 226 u32 brrl; /* Boot release */ 227 u8 res_0e8[0x100-0xe8]; 228 u32 rcwsr[16]; /* Reset control word status */ 229#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 230#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 231#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 232#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 233#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 234#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 235#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 236#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 237#define RCW_SB_EN_REG_INDEX 7 238#define RCW_SB_EN_MASK 0x00200000 239 240 u8 res_140[0x200-0x140]; 241 u32 scratchrw[4]; /* Scratch Read/Write */ 242 u8 res_210[0x300-0x210]; 243 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 244 u8 res_310[0x400-0x310]; 245 u32 crstsr[12]; 246 u8 res_430[0x500-0x430]; 247 248 /* PCI Express n Logical I/O Device Number register */ 249 u32 dcfg_ccsr_pex1liodnr; 250 u32 dcfg_ccsr_pex2liodnr; 251 u32 dcfg_ccsr_pex3liodnr; 252 u32 dcfg_ccsr_pex4liodnr; 253 /* RIO n Logical I/O Device Number register */ 254 u32 dcfg_ccsr_rio1liodnr; 255 u32 dcfg_ccsr_rio2liodnr; 256 u32 dcfg_ccsr_rio3liodnr; 257 u32 dcfg_ccsr_rio4liodnr; 258 /* USB Logical I/O Device Number register */ 259 u32 dcfg_ccsr_usb1liodnr; 260 u32 dcfg_ccsr_usb2liodnr; 261 u32 dcfg_ccsr_usb3liodnr; 262 u32 dcfg_ccsr_usb4liodnr; 263 /* SD/MMC Logical I/O Device Number register */ 264 u32 dcfg_ccsr_sdmmc1liodnr; 265 u32 dcfg_ccsr_sdmmc2liodnr; 266 u32 dcfg_ccsr_sdmmc3liodnr; 267 u32 dcfg_ccsr_sdmmc4liodnr; 268 /* RIO Message Unit Logical I/O Device Number register */ 269 u32 dcfg_ccsr_riomaintliodnr; 270 271 u8 res_544[0x550-0x544]; 272 u32 sataliodnr[4]; 273 u8 res_560[0x570-0x560]; 274 275 u32 dcfg_ccsr_misc1liodnr; 276 u32 dcfg_ccsr_misc2liodnr; 277 u32 dcfg_ccsr_misc3liodnr; 278 u32 dcfg_ccsr_misc4liodnr; 279 u32 dcfg_ccsr_dma1liodnr; 280 u32 dcfg_ccsr_dma2liodnr; 281 u32 dcfg_ccsr_dma3liodnr; 282 u32 dcfg_ccsr_dma4liodnr; 283 u32 dcfg_ccsr_spare1liodnr; 284 u32 dcfg_ccsr_spare2liodnr; 285 u32 dcfg_ccsr_spare3liodnr; 286 u32 dcfg_ccsr_spare4liodnr; 287 u8 res_5a0[0x600-0x5a0]; 288 u32 dcfg_ccsr_pblsr; 289 290 u32 pamubypenr; 291 u32 dmacr1; 292 293 u8 res_60c[0x610-0x60c]; 294 u32 dcfg_ccsr_gensr1; 295 u32 dcfg_ccsr_gensr2; 296 u32 dcfg_ccsr_gensr3; 297 u32 dcfg_ccsr_gensr4; 298 u32 dcfg_ccsr_gencr1; 299 u32 dcfg_ccsr_gencr2; 300 u32 dcfg_ccsr_gencr3; 301 u32 dcfg_ccsr_gencr4; 302 u32 dcfg_ccsr_gencr5; 303 u32 dcfg_ccsr_gencr6; 304 u32 dcfg_ccsr_gencr7; 305 u8 res_63c[0x658-0x63c]; 306 u32 dcfg_ccsr_cgensr1; 307 u32 dcfg_ccsr_cgensr0; 308 u8 res_660[0x678-0x660]; 309 u32 dcfg_ccsr_cgencr1; 310 311 u32 dcfg_ccsr_cgencr0; 312 u8 res_680[0x700-0x680]; 313 u32 dcfg_ccsr_sriopstecr; 314 u32 dcfg_ccsr_dcsrcr; 315 316 u8 res_708[0x740-0x708]; /* add more registers when needed */ 317 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 318 struct { 319 u32 upper; 320 u32 lower; 321 } tp_cluster[16]; 322 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 323 u32 dcfg_ccsr_qmbm_warmrst; 324 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 325 u32 dcfg_ccsr_reserved0; 326 u32 dcfg_ccsr_reserved1; 327}; 328 329#define SCFG_QSPI_CLKSEL 0x40100000 330#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 331#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 332#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 333#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 334#define SCFG_USBPWRFAULT_SHARED 0x00000001 335#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 336#define SCFG_USBPWRFAULT_USB3_SHIFT 4 337#define SCFG_USBPWRFAULT_USB2_SHIFT 2 338#define SCFG_USBPWRFAULT_USB1_SHIFT 0 339 340#define SCFG_BASE 0x01570000 341#define SCFG_USB3PRM1CR_USB1 0x070 342#define SCFG_USB3PRM2CR_USB1 0x074 343#define SCFG_USB3PRM1CR_USB2 0x07C 344#define SCFG_USB3PRM2CR_USB2 0x080 345#define SCFG_USB3PRM1CR_USB3 0x088 346#define SCFG_USB3PRM2CR_USB3 0x08c 347#define SCFG_USB_TXVREFTUNE 0x9 348#define SCFG_USB_SQRXTUNE_MASK 0x7 349#define SCFG_USB_PCSTXSWINGFULL 0x47 350#define SCFG_USB_PHY1 0x084F0000 351#define SCFG_USB_PHY2 0x08500000 352#define SCFG_USB_PHY3 0x08510000 353#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 354#define USB_PHY_RX_EQ_VAL_1 0x0000 355#define USB_PHY_RX_EQ_VAL_2 0x0080 356#define USB_PHY_RX_EQ_VAL_3 0x0380 357#define USB_PHY_RX_EQ_VAL_4 0x0b80 358 359#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 360#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 361#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 362#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 363 364/* Supplemental Configuration Unit */ 365struct ccsr_scfg { 366 u8 res_000[0x100-0x000]; 367 u32 usb2_icid; 368 u32 usb3_icid; 369 u8 res_108[0x114-0x108]; 370 u32 dma_icid; 371 u32 sata_icid; 372 u32 usb1_icid; 373 u32 qe_icid; 374 u32 sdhc_icid; 375 u32 edma_icid; 376 u32 etr_icid; 377 u32 core_sft_rst[4]; 378 u8 res_140[0x158-0x140]; 379 u32 altcbar; 380 u32 qspi_cfg; 381 u8 res_160[0x180-0x160]; 382 u32 dmamcr; 383 u8 res_184[0x188-0x184]; 384 u32 gic_align; 385 u32 debug_icid; 386 u8 res_190[0x1a4-0x190]; 387 u32 snpcnfgcr; 388 u8 res_1a8[0x1ac-0x1a8]; 389 u32 intpcr; 390 u8 res_1b0[0x204-0x1b0]; 391 u32 coresrencr; 392 u8 res_208[0x220-0x208]; 393 u32 rvbar0_0; 394 u32 rvbar0_1; 395 u32 rvbar1_0; 396 u32 rvbar1_1; 397 u32 rvbar2_0; 398 u32 rvbar2_1; 399 u32 rvbar3_0; 400 u32 rvbar3_1; 401 u32 lpmcsr; 402 u8 res_244[0x400-0x244]; 403 u32 qspidqscr; 404 u32 ecgtxcmcr; 405 u32 sdhciovselcr; 406 u32 rcwpmuxcr0; 407 u32 usbdrvvbus_selcr; 408 u32 usbpwrfault_selcr; 409 u32 usb_refclk_selcr1; 410 u32 usb_refclk_selcr2; 411 u32 usb_refclk_selcr3; 412 u8 res_424[0x600-0x424]; 413 u32 scratchrw[4]; 414 u8 res_610[0x680-0x610]; 415 u32 corebcr; 416 u8 res_684[0x1000-0x684]; 417 u32 pex1msiir; 418 u32 pex1msir; 419 u8 res_1008[0x2000-0x1008]; 420 u32 pex2; 421 u32 pex2msir; 422 u8 res_2008[0x3000-0x2008]; 423 u32 pex3msiir; 424 u32 pex3msir; 425}; 426 427/* Clocking */ 428struct ccsr_clk { 429 struct { 430 u32 clkcncsr; /* core cluster n clock control status */ 431 u8 res_004[0x0c]; 432 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 433 u8 res_014[0x0c]; 434 } clkcsr[4]; 435 u8 res_040[0x780]; /* 0x100 */ 436 struct { 437 u32 pllcngsr; 438 u8 res_804[0x1c]; 439 } pllcgsr[2]; 440 u8 res_840[0x1c0]; 441 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 442 u8 res_a04[0x1fc]; 443 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 444 u8 res_c04[0x1c]; 445 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 446 u8 res_c24[0x3dc]; 447}; 448 449/* System Counter */ 450struct sctr_regs { 451 u32 cntcr; 452 u32 cntsr; 453 u32 cntcv1; 454 u32 cntcv2; 455 u32 resv1[4]; 456 u32 cntfid0; 457 u32 cntfid1; 458 u32 resv2[1002]; 459 u32 counterid[12]; 460}; 461 462#define SRDS_MAX_LANES 4 463struct ccsr_serdes { 464 struct { 465 u32 rstctl; /* Reset Control Register */ 466#define SRDS_RSTCTL_RST 0x80000000 467#define SRDS_RSTCTL_RSTDONE 0x40000000 468#define SRDS_RSTCTL_RSTERR 0x20000000 469#define SRDS_RSTCTL_SWRST 0x10000000 470#define SRDS_RSTCTL_SDEN 0x00000020 471#define SRDS_RSTCTL_SDRST_B 0x00000040 472#define SRDS_RSTCTL_PLLRST_B 0x00000080 473 u32 pllcr0; /* PLL Control Register 0 */ 474#define SRDS_PLLCR0_POFF 0x80000000 475#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 476#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 477#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 478#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 479#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 480#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 481#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 482#define SRDS_PLLCR0_PLL_LCK 0x00800000 483#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 484#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 485#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 486#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 487#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 488#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 489#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 490 u32 pllcr1; /* PLL Control Register 1 */ 491#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 492 u32 res_0c; /* 0x00c */ 493 u32 pllcr3; 494 u32 pllcr4; 495 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 496 u8 res_1c[0x20-0x1c]; 497 } bank[2]; 498 u8 res_40[0x90-0x40]; 499 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 500 u8 res_94[0xa0-0x94]; 501 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 502 u8 res_a4[0xb0-0xa4]; 503 u32 srdsgr0; /* 0xb0 General Register 0 */ 504 u8 res_b4[0x100-0xb4]; 505 struct { 506 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 507 u8 res_104[0x120-0x104]; 508 } lnpssr[4]; /* Lane A, B, C, D */ 509 u8 res_180[0x200-0x180]; 510 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 511 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 512 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 513 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 514 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 515 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 516 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 517 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 518 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 519 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 520 u32 srdspccra; /* 0x228 Protocol Configuration A */ 521 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 522 u8 res_230[0x800-0x230]; 523 struct { 524 u32 gcr0; /* 0x800 General Control Register 0 */ 525 u32 gcr1; /* 0x804 General Control Register 1 */ 526 u32 gcr2; /* 0x808 General Control Register 2 */ 527 u32 sscr0; 528 u32 recr0; /* 0x810 Receive Equalization Control */ 529 u32 recr1; 530 u32 tecr0; /* 0x818 Transmit Equalization Control */ 531 u32 sscr1; 532 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 533 u8 res_824[0x83c-0x824]; 534 u32 tcsr3; 535 } lane[4]; /* Lane A, B, C, D */ 536 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 537 struct { 538 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 539 u8 res_1004[0x1040-0x1004]; 540 } pcie[3]; 541 u8 res_10c0[0x1800-0x10c0]; 542 struct { 543 u8 res_1800[0x1804-0x1800]; 544 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 545 u8 res_1808[0x180c-0x1808]; 546 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 547 } sgmii[4]; /* Lane A, B, C, D */ 548 u8 res_1840[0x1880-0x1840]; 549 struct { 550 u8 res_1880[0x1884-0x1880]; 551 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 552 u8 res_1888[0x188c-0x1888]; 553 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 554 } qsgmii[2]; /* Lane A, B */ 555 u8 res_18a0[0x1980-0x18a0]; 556 struct { 557 u8 res_1980[0x1984-0x1980]; 558 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 559 u8 res_1988[0x198c-0x1988]; 560 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 561 } xfi[2]; /* Lane A, B */ 562 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 563}; 564 565/* MMU 500 */ 566#define SMMU_SCR0 (SMMU_BASE + 0x0) 567#define SMMU_SCR1 (SMMU_BASE + 0x4) 568#define SMMU_SCR2 (SMMU_BASE + 0x8) 569#define SMMU_SACR (SMMU_BASE + 0x10) 570#define SMMU_IDR0 (SMMU_BASE + 0x20) 571#define SMMU_IDR1 (SMMU_BASE + 0x24) 572 573#define SMMU_NSCR0 (SMMU_BASE + 0x400) 574#define SMMU_NSCR2 (SMMU_BASE + 0x408) 575#define SMMU_NSACR (SMMU_BASE + 0x410) 576 577#define SCR0_CLIENTPD_MASK 0x00000001 578#define SCR0_USFCFG_MASK 0x00000400 579 580uint get_svr(void); 581 582#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 583