1/* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 8#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 9 10#define MXC_CCM_BASE CCM_BASE_ADDR 11 12/* DPLL register mapping structure */ 13struct mxc_pll_reg { 14 u32 ctrl; 15 u32 config; 16 u32 op; 17 u32 mfd; 18 u32 mfn; 19 u32 mfn_minus; 20 u32 mfn_plus; 21 u32 hfs_op; 22 u32 hfs_mfd; 23 u32 hfs_mfn; 24 u32 mfn_togc; 25 u32 destat; 26}; 27 28/* Register maping of CCM*/ 29struct mxc_ccm_reg { 30 u32 ccr; /* 0x0000 */ 31 u32 ccdr; 32 u32 csr; 33 u32 ccsr; 34 u32 cacrr; /* 0x0010*/ 35 u32 cbcdr; 36 u32 cbcmr; 37 u32 cscmr1; 38 u32 cscmr2; /* 0x0020 */ 39 u32 cscdr1; 40 u32 cs1cdr; 41 u32 cs2cdr; 42 u32 cdcdr; /* 0x0030 */ 43 u32 chsccdr; 44 u32 cscdr2; 45 u32 cscdr3; 46 u32 cscdr4; /* 0x0040 */ 47 u32 cwdr; 48 u32 cdhipr; 49 u32 cdcr; 50 u32 ctor; /* 0x0050 */ 51 u32 clpcr; 52 u32 cisr; 53 u32 cimr; 54 u32 ccosr; /* 0x0060 */ 55 u32 cgpr; 56 u32 CCGR0; 57 u32 CCGR1; 58 u32 CCGR2; /* 0x0070 */ 59 u32 CCGR3; 60 u32 CCGR4; 61 u32 CCGR5; 62 u32 CCGR6; /* 0x0080 */ 63#ifdef CONFIG_MX53 64 u32 CCGR7; /* 0x0084 */ 65#endif 66 u32 cmeor; 67}; 68 69/* Define the bits in register CCR */ 70#define MXC_CCM_CCR_COSC_EN (0x1 << 12) 71#if defined(CONFIG_MX51) 72#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) 73#endif 74#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) 75#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) 76#if defined(CONFIG_MX51) 77#define MXC_CCM_CCR_FPM_EN (0x1 << 8) 78#endif 79#define MXC_CCM_CCR_OSCNT_OFFSET 0 80#define MXC_CCM_CCR_OSCNT_MASK 0xFF 81#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) 82#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) 83 84/* Define the bits in register CCSR */ 85#if defined(CONFIG_MX51) 86#define MXC_CCM_CCSR_LP_APM (0x1 << 9) 87#elif defined(CONFIG_MX53) 88#define MXC_CCM_CCSR_LP_APM (0x1 << 10) 89#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) 90#endif 91#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 92#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) 93#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) 94#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) 95#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 96#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) 97#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) 98#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) 99#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 100#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) 101#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) 102#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) 103#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) 104#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) 105#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 106 107/* Define the bits in register CACRR */ 108#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 109#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 110#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) 111#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) 112 113/* Define the bits in register CBCDR */ 114#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) 115#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 116#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) 117#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) 118#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) 119#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 120#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 121#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 122#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 123#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) 124#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) 125#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 126#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 127#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) 128#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) 129#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 130#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 131#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) 132#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) 133#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 134#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 135#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) 136#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) 137#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 138#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 139#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) 140#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) 141#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 142#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 143#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) 144#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) 145#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 146#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 147#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) 148#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) 149#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 150#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 151#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) 152#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) 153#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 154#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 155#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) 156#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) 157 158/* Define the bits in register CSCMR1 */ 159#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 160#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 161#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) 162#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) 163#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 164#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 165#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) 166#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) 167#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 168#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 169#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 170#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) 171#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) 172#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 173#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 174#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) 175#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) 176#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 177#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 178#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) 179#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) 180#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 181#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 182#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 183#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 184#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) 185#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) 186#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 187#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 188#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) 189#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 190#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 191#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 192#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) 193#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 194#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 195#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 196#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 197#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 198#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) 199#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 200#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 201#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 202#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 203#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 204#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) 205#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 206#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 207#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 208#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) 209#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) 210#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 211#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 212 213/* Define the bits in register CSCMR2 */ 214#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 215#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) 216#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) 217#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) 218 219#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 220 221/* Define the bits in register CSCDR2 */ 222#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 223#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 224#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) 225#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) 226#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 227#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 228#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) 229#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) 230#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 231#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 232#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) 233#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 234#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 235#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 236#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) 237#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) 238#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 239#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) 240#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) 241#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) 242#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 243#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F 244#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) 245#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) 246 247/* Define the bits in register CBCMR */ 248#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 249#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 250#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) 251#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 252#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 253#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 254#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) 255#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 256#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 257#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 258#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) 259#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) 260#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 261#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 262#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) 263#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 264#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 265#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 266#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) 267#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) 268#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 269#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 270#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) 271#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 272#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 273#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 274 275/* Define the bits in register CSCDR1 */ 276#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 277#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 278#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) 279#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) 280#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 281#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 282#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) 283#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) 284#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 285#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 286#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) 287#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 288#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 289#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 290#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) 291#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) 292#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 293#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 294#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) 295#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) 296#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 297#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 298#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) 299#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) 300#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 301#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 302#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) 303#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) 304#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 305#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 306#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) 307#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) 308#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 309#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 310#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) 311#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) 312 313/* Define the bits in register CCDR */ 314#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) 315 316/* Define the bits in register CGPR */ 317#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 318 319/* Define the bits in register CCGRx */ 320#define MXC_CCM_CCGR_CG_MASK 0x3 321#define MXC_CCM_CCGR_CG_OFF 0x0 322#define MXC_CCM_CCGR_CG_RUN_ON 0x1 323#define MXC_CCM_CCGR_CG_ON 0x3 324 325#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 326#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) 327#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 328#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) 329#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 330#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) 331#define MXC_CCM_CCGR0_TZIC_OFFSET 6 332#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) 333#define MXC_CCM_CCGR0_DAP_OFFSET 8 334#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) 335#define MXC_CCM_CCGR0_TPIU_OFFSET 10 336#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) 337#define MXC_CCM_CCGR0_CTI2_OFFSET 12 338#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) 339#define MXC_CCM_CCGR0_CTI3_OFFSET 14 340#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) 341#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 342#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) 343#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 344#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) 345#define MXC_CCM_CCGR0_ROMCP_OFFSET 20 346#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) 347#define MXC_CCM_CCGR0_ROM_OFFSET 22 348#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) 349#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 350#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) 351#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 352#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) 353#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 354#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) 355#define MXC_CCM_CCGR0_IIM_OFFSET 30 356#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) 357 358#define MXC_CCM_CCGR1_TMAX1_OFFSET 0 359#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) 360#define MXC_CCM_CCGR1_TMAX2_OFFSET 2 361#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) 362#define MXC_CCM_CCGR1_TMAX3_OFFSET 4 363#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) 364#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 365#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) 366#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 367#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) 368#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 369#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) 370#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 371#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) 372#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 373#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) 374#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 375#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) 376#define MXC_CCM_CCGR1_I2C1_OFFSET 18 377#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) 378#define MXC_CCM_CCGR1_I2C2_OFFSET 20 379#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) 380#if defined(CONFIG_MX51) 381#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 382#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) 383#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 384#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) 385#elif defined(CONFIG_MX53) 386#define MXC_CCM_CCGR1_I2C3_OFFSET 22 387#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) 388#endif 389#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 390#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) 391#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 392#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) 393#define MXC_CCM_CCGR1_SCC_OFFSET 30 394#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) 395 396#if defined(CONFIG_MX51) 397#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 398#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) 399#endif 400#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 401#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) 402#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 403#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) 404#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 405#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) 406#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 407#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) 408#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 409#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) 410#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 411#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) 412#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 413#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) 414#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 415#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) 416#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 417#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) 418#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 419#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) 420#define MXC_CCM_CCGR2_OWIRE_OFFSET 22 421#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) 422#define MXC_CCM_CCGR2_FEC_OFFSET 24 423#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) 424#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 425#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) 426#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 427#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) 428#define MXC_CCM_CCGR2_TVE_OFFSET 30 429#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) 430 431#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 432#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) 433#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 434#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) 435#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 436#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) 437#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 438#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) 439#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 440#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) 441#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 442#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) 443#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 444#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) 445#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 446#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) 447#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 448#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) 449#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 450#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) 451#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 452#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) 453#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 454#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) 455#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 456#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) 457#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 458#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) 459#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 460#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) 461#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 462#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) 463 464#define MXC_CCM_CCGR4_PATA_OFFSET 0 465#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) 466#if defined(CONFIG_MX51) 467#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 468#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) 469#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 470#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) 471#elif defined(CONFIG_MX53) 472#define MXC_CCM_CCGR4_SATA_OFFSET 2 473#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) 474#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 475#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) 476#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 477#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) 478#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 479#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) 480#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 481#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) 482#endif 483#define MXC_CCM_CCGR4_SAHARA_OFFSET 14 484#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) 485#define MXC_CCM_CCGR4_RTIC_OFFSET 16 486#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) 487#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 488#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) 489#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 490#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) 491#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 492#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) 493#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 494#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) 495#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 496#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) 497#define MXC_CCM_CCGR4_SRTC_OFFSET 28 498#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) 499#define MXC_CCM_CCGR4_SDMA_OFFSET 30 500#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) 501 502#define MXC_CCM_CCGR5_SPBA_OFFSET 0 503#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) 504#define MXC_CCM_CCGR5_GPU_OFFSET 2 505#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) 506#define MXC_CCM_CCGR5_GARB_OFFSET 4 507#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) 508#define MXC_CCM_CCGR5_VPU_OFFSET 6 509#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) 510#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 511#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) 512#define MXC_CCM_CCGR5_IPU_OFFSET 10 513#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) 514#if defined(CONFIG_MX51) 515#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 516#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) 517#elif defined(CONFIG_MX53) 518#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 519#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) 520#endif 521#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 522#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) 523#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 524#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) 525#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 526#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) 527#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 528#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) 529#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 530#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) 531#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 532#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) 533#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 534#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) 535#if defined(CONFIG_MX51) 536#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 537#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) 538#endif 539#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 540#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) 541 542#if defined(CONFIG_MX53) 543#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 544#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) 545#define MXC_CCM_CCGR6_OCRAM_OFFSET 2 546#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) 547#endif 548#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 549#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) 550#if defined(CONFIG_MX51) 551#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 552#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) 553#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 554#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) 555#elif defined(CONFIG_MX53) 556#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 557#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) 558#endif 559#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 560#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) 561#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 562#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) 563#define MXC_CCM_CCGR6_GPU2D_OFFSET 14 564#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) 565#if defined(CONFIG_MX53) 566#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 567#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) 568#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 569#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) 570#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 571#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) 572#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 573#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) 574#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 575#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) 576#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 577#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) 578#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 579#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) 580#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 581#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) 582 583#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 584#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) 585#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 586#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) 587#define MXC_CCM_CCGR7_MLB_OFFSET 4 588#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) 589#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 590#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) 591#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 592#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) 593#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 594#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) 595#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 596#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) 597#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 598#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) 599#endif 600 601/* Define the bits in register CLPCR */ 602#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 603 604#define MXC_DPLLC_CTL_HFSM (1 << 7) 605#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) 606 607#define MXC_DPLLC_OP_PDF_MASK 0xf 608#define MXC_DPLLC_OP_MFI_OFFSET 4 609#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) 610#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) 611#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) 612 613#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff 614 615#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff 616 617#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 618