1/* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __ASM_ARCH_MX6SX_DDR_H__ 8#define __ASM_ARCH_MX6SX_DDR_H__ 9 10#ifndef CONFIG_MX6SX 11#error "wrong CPU" 12#endif 13 14#define MX6_IOM_DRAM_DQM0 0x020e02ec 15#define MX6_IOM_DRAM_DQM1 0x020e02f0 16#define MX6_IOM_DRAM_DQM2 0x020e02f4 17#define MX6_IOM_DRAM_DQM3 0x020e02f8 18 19#define MX6_IOM_DRAM_RAS 0x020e02fc 20#define MX6_IOM_DRAM_CAS 0x020e0300 21#define MX6_IOM_DRAM_SDODT0 0x020e0310 22#define MX6_IOM_DRAM_SDODT1 0x020e0314 23#define MX6_IOM_DRAM_SDBA2 0x020e0320 24#define MX6_IOM_DRAM_SDCKE0 0x020e0324 25#define MX6_IOM_DRAM_SDCKE1 0x020e0328 26#define MX6_IOM_DRAM_SDCLK_0 0x020e032c 27#define MX6_IOM_DRAM_RESET 0x020e0340 28 29#define MX6_IOM_DRAM_SDQS0 0x020e0330 30#define MX6_IOM_DRAM_SDQS1 0x020e0334 31#define MX6_IOM_DRAM_SDQS2 0x020e0338 32#define MX6_IOM_DRAM_SDQS3 0x020e033c 33 34#define MX6_IOM_GRP_ADDDS 0x020e05f4 35#define MX6_IOM_DDRMODE_CTL 0x020e05f8 36#define MX6_IOM_GRP_DDRPKE 0x020e05fc 37#define MX6_IOM_GRP_DDRMODE 0x020e0608 38#define MX6_IOM_GRP_B0DS 0x020e060c 39#define MX6_IOM_GRP_B1DS 0x020e0610 40#define MX6_IOM_GRP_CTLDS 0x020e0614 41#define MX6_IOM_GRP_DDR_TYPE 0x020e0618 42#define MX6_IOM_GRP_B2DS 0x020e061c 43#define MX6_IOM_GRP_B3DS 0x020e0620 44 45#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ 46