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6#ifndef _ASM_ARCH_GRF_RK3036_H
7#define _ASM_ARCH_GRF_RK3036_H
8
9#include <common.h>
10
11struct rk3036_grf {
12 unsigned int reserved[0x2a];
13 unsigned int gpio0a_iomux;
14 unsigned int gpio0b_iomux;
15 unsigned int gpio0c_iomux;
16 unsigned int gpio0d_iomux;
17
18 unsigned int gpio1a_iomux;
19 unsigned int gpio1b_iomux;
20 unsigned int gpio1c_iomux;
21 unsigned int gpio1d_iomux;
22
23 unsigned int gpio2a_iomux;
24 unsigned int gpio2b_iomux;
25 unsigned int gpio2c_iomux;
26 unsigned int gpio2d_iomux;
27
28 unsigned int reserved2[0x0a];
29 unsigned int gpiods;
30 unsigned int reserved3[0x05];
31 unsigned int gpio0l_pull;
32 unsigned int gpio0h_pull;
33 unsigned int gpio1l_pull;
34 unsigned int gpio1h_pull;
35 unsigned int gpio2l_pull;
36 unsigned int gpio2h_pull;
37 unsigned int reserved4[4];
38 unsigned int soc_con0;
39 unsigned int soc_con1;
40 unsigned int soc_con2;
41 unsigned int soc_status0;
42 unsigned int reserved5;
43 unsigned int soc_con3;
44 unsigned int reserved6;
45 unsigned int dmac_con0;
46 unsigned int dmac_con1;
47 unsigned int dmac_con2;
48 unsigned int reserved7[5];
49 unsigned int uoc0_con5;
50 unsigned int reserved8[4];
51 unsigned int uoc1_con4;
52 unsigned int uoc1_con5;
53 unsigned int reserved9;
54 unsigned int ddrc_stat;
55 unsigned int uoc_con6;
56 unsigned int soc_status1;
57 unsigned int cpu_con0;
58 unsigned int cpu_con1;
59 unsigned int cpu_con2;
60 unsigned int cpu_con3;
61 unsigned int reserved10;
62 unsigned int reserved11;
63 unsigned int cpu_status0;
64 unsigned int cpu_status1;
65 unsigned int os_reg[8];
66 unsigned int reserved12[6];
67 unsigned int dll_con[4];
68 unsigned int dll_status[4];
69 unsigned int dfi_wrnum;
70 unsigned int dfi_rdnum;
71 unsigned int dfi_actnum;
72 unsigned int dfi_timerval;
73 unsigned int nfi_fifo[4];
74 unsigned int reserved13[0x10];
75 unsigned int usbphy0_con[8];
76 unsigned int usbphy1_con[8];
77 unsigned int reserved14[0x10];
78 unsigned int chip_tag;
79 unsigned int sdmmc_det_cnt;
80};
81check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
82
83
84enum {
85 GPIO0A3_SHIFT = 6,
86 GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
87 GPIO0A3_GPIO = 0,
88 GPIO0A3_I2C1_SDA,
89
90 GPIO0A2_SHIFT = 4,
91 GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
92 GPIO0A2_GPIO = 0,
93 GPIO0A2_I2C1_SCL,
94
95 GPIO0A1_SHIFT = 2,
96 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
97 GPIO0A1_GPIO = 0,
98 GPIO0A1_I2C0_SDA,
99 GPIO0A1_PWM2,
100
101 GPIO0A0_SHIFT = 0,
102 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
103 GPIO0A0_GPIO = 0,
104 GPIO0A0_I2C0_SCL,
105 GPIO0A0_PWM1,
106};
107
108
109enum {
110 GPIO0B6_SHIFT = 12,
111 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
112 GPIO0B6_GPIO = 0,
113 GPIO0B6_MMC1_D3,
114 GPIO0B6_I2S1_SCLK,
115
116 GPIO0B5_SHIFT = 10,
117 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
118 GPIO0B5_GPIO = 0,
119 GPIO0B5_MMC1_D2,
120 GPIO0B5_I2S1_SDI,
121
122 GPIO0B4_SHIFT = 8,
123 GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
124 GPIO0B4_GPIO = 0,
125 GPIO0B4_MMC1_D1,
126 GPIO0B4_I2S1_LRCKTX,
127
128 GPIO0B3_SHIFT = 6,
129 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
130 GPIO0B3_GPIO = 0,
131 GPIO0B3_MMC1_D0,
132 GPIO0B3_I2S1_LRCKRX,
133
134 GPIO0B1_SHIFT = 2,
135 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
136 GPIO0B1_GPIO = 0,
137 GPIO0B1_MMC1_CLKOUT,
138 GPIO0B1_I2S1_MCLK,
139
140 GPIO0B0_SHIFT = 0,
141 GPIO0B0_MASK = 3,
142 GPIO0B0_GPIO = 0,
143 GPIO0B0_MMC1_CMD,
144 GPIO0B0_I2S1_SDO,
145};
146
147
148enum {
149 GPIO0C4_SHIFT = 8,
150 GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
151 GPIO0C4_GPIO = 0,
152 GPIO0C4_DRIVE_VBUS,
153
154 GPIO0C3_SHIFT = 6,
155 GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
156 GPIO0C3_GPIO = 0,
157 GPIO0C3_UART0_CTSN,
158
159 GPIO0C2_SHIFT = 4,
160 GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
161 GPIO0C2_GPIO = 0,
162 GPIO0C2_UART0_RTSN,
163
164 GPIO0C1_SHIFT = 2,
165 GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
166 GPIO0C1_GPIO = 0,
167 GPIO0C1_UART0_SIN,
168
169
170 GPIO0C0_SHIFT = 0,
171 GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
172 GPIO0C0_GPIO = 0,
173 GPIO0C0_UART0_SOUT,
174};
175
176
177enum {
178 GPIO0D4_SHIFT = 8,
179 GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
180 GPIO0D4_GPIO = 0,
181 GPIO0D4_SPDIF,
182
183 GPIO0D3_SHIFT = 6,
184 GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
185 GPIO0D3_GPIO = 0,
186 GPIO0D3_PWM3,
187
188 GPIO0D2_SHIFT = 4,
189 GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
190 GPIO0D2_GPIO = 0,
191 GPIO0D2_PWM0,
192};
193
194
195enum {
196 GPIO1A5_SHIFT = 10,
197 GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
198 GPIO1A5_GPIO = 0,
199 GPIO1A5_I2S_SDI,
200
201 GPIO1A4_SHIFT = 8,
202 GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
203 GPIO1A4_GPIO = 0,
204 GPIO1A4_I2S_SD0,
205
206 GPIO1A3_SHIFT = 6,
207 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
208 GPIO1A3_GPIO = 0,
209 GPIO1A3_I2S_LRCKTX,
210
211 GPIO1A2_SHIFT = 4,
212 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
213 GPIO1A2_GPIO = 0,
214 GPIO1A2_I2S_LRCKRX,
215 GPIO1A2_PWM1_0,
216
217 GPIO1A1_SHIFT = 2,
218 GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
219 GPIO1A1_GPIO = 0,
220 GPIO1A1_I2S_SCLK,
221
222 GPIO1A0_SHIFT = 0,
223 GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
224 GPIO1A0_GPIO = 0,
225 GPIO1A0_I2S_MCLK,
226
227};
228
229
230enum {
231 GPIO1B7_SHIFT = 14,
232 GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
233 GPIO1B7_GPIO = 0,
234 GPIO1B7_MMC0_CMD,
235
236 GPIO1B3_SHIFT = 6,
237 GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
238 GPIO1B3_GPIO = 0,
239 GPIO1B3_HDMI_HPD,
240
241 GPIO1B2_SHIFT = 4,
242 GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
243 GPIO1B2_GPIO = 0,
244 GPIO1B2_HDMI_SCL,
245
246 GPIO1B1_SHIFT = 2,
247 GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
248 GPIO1B1_GPIO = 0,
249 GPIO1B1_HDMI_SDA,
250
251 GPIO1B0_SHIFT = 0,
252 GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
253 GPIO1B0_GPIO = 0,
254 GPIO1B0_HDMI_CEC,
255};
256
257
258enum {
259 GPIO1C5_SHIFT = 10,
260 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
261 GPIO1C5_GPIO = 0,
262 GPIO1C5_MMC0_D3,
263 GPIO1C5_JTAG_TMS,
264
265 GPIO1C4_SHIFT = 8,
266 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
267 GPIO1C4_GPIO = 0,
268 GPIO1C4_MMC0_D2,
269 GPIO1C4_JTAG_TCK,
270
271 GPIO1C3_SHIFT = 6,
272 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
273 GPIO1C3_GPIO = 0,
274 GPIO1C3_MMC0_D1,
275 GPIO1C3_UART2_SOUT,
276
277 GPIO1C2_SHIFT = 4,
278 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
279 GPIO1C2_GPIO = 0,
280 GPIO1C2_MMC0_D0,
281 GPIO1C2_UART2_SIN,
282
283 GPIO1C1_SHIFT = 2,
284 GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
285 GPIO1C1_GPIO = 0,
286 GPIO1C1_MMC0_DETN,
287
288 GPIO1C0_SHIFT = 0,
289 GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
290 GPIO1C0_GPIO = 0,
291 GPIO1C0_MMC0_CLKOUT,
292};
293
294
295enum {
296 GPIO1D7_SHIFT = 14,
297 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
298 GPIO1D7_GPIO = 0,
299 GPIO1D7_NAND_D7,
300 GPIO1D7_EMMC_D7,
301 GPIO1D7_SPI_CSN1,
302
303 GPIO1D6_SHIFT = 12,
304 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
305 GPIO1D6_GPIO = 0,
306 GPIO1D6_NAND_D6,
307 GPIO1D6_EMMC_D6,
308 GPIO1D6_SPI_CSN0,
309
310 GPIO1D5_SHIFT = 10,
311 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
312 GPIO1D5_GPIO = 0,
313 GPIO1D5_NAND_D5,
314 GPIO1D5_EMMC_D5,
315 GPIO1D5_SPI_TXD,
316
317 GPIO1D4_SHIFT = 8,
318 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
319 GPIO1D4_GPIO = 0,
320 GPIO1D4_NAND_D4,
321 GPIO1D4_EMMC_D4,
322 GPIO1D4_SPI_RXD,
323
324 GPIO1D3_SHIFT = 6,
325 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
326 GPIO1D3_GPIO = 0,
327 GPIO1D3_NAND_D3,
328 GPIO1D3_EMMC_D3,
329 GPIO1D3_SFC_SIO3,
330
331 GPIO1D2_SHIFT = 4,
332 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
333 GPIO1D2_GPIO = 0,
334 GPIO1D2_NAND_D2,
335 GPIO1D2_EMMC_D2,
336 GPIO1D2_SFC_SIO2,
337
338 GPIO1D1_SHIFT = 2,
339 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
340 GPIO1D1_GPIO = 0,
341 GPIO1D1_NAND_D1,
342 GPIO1D1_EMMC_D1,
343 GPIO1D1_SFC_SIO1,
344
345 GPIO1D0_SHIFT = 0,
346 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
347 GPIO1D0_GPIO = 0,
348 GPIO1D0_NAND_D0,
349 GPIO1D0_EMMC_D0,
350 GPIO1D0_SFC_SIO0,
351};
352
353
354enum {
355 GPIO2A7_SHIFT = 14,
356 GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
357 GPIO2A7_GPIO = 0,
358 GPIO2A7_TESTCLK_OUT,
359
360 GPIO2A6_SHIFT = 12,
361 GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
362 GPIO2A6_GPIO = 0,
363 GPIO2A6_NAND_CS0,
364
365 GPIO2A4_SHIFT = 8,
366 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
367 GPIO2A4_GPIO = 0,
368 GPIO2A4_NAND_RDY,
369 GPIO2A4_EMMC_CMD,
370 GPIO2A3_SFC_CLK,
371
372 GPIO2A3_SHIFT = 6,
373 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
374 GPIO2A3_GPIO = 0,
375 GPIO2A3_NAND_RDN,
376 GPIO2A4_SFC_CSN1,
377
378 GPIO2A2_SHIFT = 4,
379 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
380 GPIO2A2_GPIO = 0,
381 GPIO2A2_NAND_WRN,
382 GPIO2A4_SFC_CSN0,
383
384 GPIO2A1_SHIFT = 2,
385 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
386 GPIO2A1_GPIO = 0,
387 GPIO2A1_NAND_CLE,
388 GPIO2A1_EMMC_CLKOUT,
389
390 GPIO2A0_SHIFT = 0,
391 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
392 GPIO2A0_GPIO = 0,
393 GPIO2A0_NAND_ALE,
394 GPIO2A0_SPI_CLK,
395};
396
397
398enum {
399 GPIO2B7_SHIFT = 14,
400 GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
401 GPIO2B7_GPIO = 0,
402 GPIO2B7_MAC_RXER,
403
404 GPIO2B6_SHIFT = 12,
405 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
406 GPIO2B6_GPIO = 0,
407 GPIO2B6_MAC_CLKOUT,
408 GPIO2B6_MAC_CLKIN,
409
410 GPIO2B5_SHIFT = 10,
411 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
412 GPIO2B5_GPIO = 0,
413 GPIO2B5_MAC_TXEN,
414
415 GPIO2B4_SHIFT = 8,
416 GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
417 GPIO2B4_GPIO = 0,
418 GPIO2B4_MAC_MDIO,
419
420 GPIO2B2_SHIFT = 4,
421 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
422 GPIO2B2_GPIO = 0,
423 GPIO2B2_MAC_CRS,
424};
425
426
427enum {
428 GPIO2C7_SHIFT = 14,
429 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
430 GPIO2C7_GPIO = 0,
431 GPIO2C7_UART1_SOUT,
432 GPIO2C7_TESTCLK_OUT1,
433
434 GPIO2C6_SHIFT = 12,
435 GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
436 GPIO2C6_GPIO = 0,
437 GPIO2C6_UART1_SIN,
438
439 GPIO2C5_SHIFT = 10,
440 GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
441 GPIO2C5_GPIO = 0,
442 GPIO2C5_I2C2_SCL,
443
444 GPIO2C4_SHIFT = 8,
445 GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
446 GPIO2C4_GPIO = 0,
447 GPIO2C4_I2C2_SDA,
448
449 GPIO2C3_SHIFT = 6,
450 GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
451 GPIO2C3_GPIO = 0,
452 GPIO2C3_MAC_TXD0,
453
454 GPIO2C2_SHIFT = 4,
455 GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
456 GPIO2C2_GPIO = 0,
457 GPIO2C2_MAC_TXD1,
458
459 GPIO2C1_SHIFT = 2,
460 GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
461 GPIO2C1_GPIO = 0,
462 GPIO2C1_MAC_RXD0,
463
464 GPIO2C0_SHIFT = 0,
465 GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
466 GPIO2C0_GPIO = 0,
467 GPIO2C0_MAC_RXD1,
468};
469
470
471enum {
472 GPIO2D6_SHIFT = 12,
473 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
474 GPIO2D6_GPIO = 0,
475 GPIO2D6_I2S_SDO1,
476
477 GPIO2D5_SHIFT = 10,
478 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
479 GPIO2D5_GPIO = 0,
480 GPIO2D5_I2S_SDO2,
481
482 GPIO2D4_SHIFT = 8,
483 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
484 GPIO2D4_GPIO = 0,
485 GPIO2D4_I2S_SDO3,
486
487 GPIO2D1_SHIFT = 2,
488 GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,
489 GPIO2D1_GPIO = 0,
490 GPIO2D1_MAC_MDC,
491};
492#endif
493
