1/* 2 * Copyright (C) 2013,2014 Renesas Electronics Corporation 3 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8#ifndef __EHCI_RMOBILE_H__ 9#define __EHCI_RMOBILE_H__ 10 11/* Register offset */ 12#define OHCI_OFFSET 0x00 13#define OHCI_SIZE 0x1000 14#define EHCI_OFFSET 0x1000 15#define EHCI_SIZE 0x1000 16 17#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) 18 19/* USBCTR */ 20#define DIRPD (1 << 8) 21#define PLL_RST (1 << 2) 22#define PCICLK_MASK (1 << 1) 23#define USBH_RST (1 << 0) 24 25/* CMND_STS */ 26#define SERREN (1 << 8) 27#define PERREN (1 << 6) 28#define MASTEREN (1 << 2) 29#define MEMEN (1 << 1) 30 31/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ 32#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) 33 34/* AHBPCI_WIN1_CTR */ 35#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) 36#define AHB_CFG_AHBPCI 0x40000000 37#define AHB_CFG_HOST 0x80000000 38 39/* AHBPCI_WIN2_CTR */ 40#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) 41 42/* PCI_INT_ENABLE */ 43#define USBH_PMEEN (1 << 19) 44#define USBH_INTBEN (1 << 17) 45#define USBH_INTAEN (1 << 16) 46 47/* AHB_BUS_CTR */ 48#define SMODE_READY_CTR (1 << 17) 49#define SMODE_READ_BURST (1 << 16) 50#define MMODE_HBUSREQ (1 << 7) 51#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) 52#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) 53#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) 54#define MMODE_WR_INCR (1 << 2) 55#define MMODE_BYTE_BURST (1 << 1) 56#define MMODE_HTRANS (1 << 0) 57 58/* PCI_ARBITER_CTR */ 59#define PCIBUS_PARK_TIMER 0x00FF0000 60#define PCIBUS_PARK_TIMER_SET 0x00070000 61#define PCIBP_MODE (1 << 12) 62#define PCIREQ7 (1 << 7) 63#define PCIREQ6 (1 << 6) 64#define PCIREQ5 (1 << 5) 65#define PCIREQ4 (1 << 4) 66#define PCIREQ3 (1 << 3) 67#define PCIREQ2 (1 << 2) 68#define PCIREQ1 (1 << 1) 69#define PCIREQ0 (1 << 0) 70 71#define SMSTPCR7 0xE615014C 72#define SMSTPCR703 (1 << 3) 73 74/* Init AHB master and slave functions of the host logic */ 75#define AHB_BUS_CTR_INIT \ 76 (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ 77 MMODE_BYTE_BURST | MMODE_HTRANS) 78 79#define USBCTR_WIN_SIZE_1GB 0x800 80 81/* PCI Configuration Registers */ 82#define PCI_CONF_OHCI_OFFSET 0x10000 83#define PCI_CONF_EHCI_OFFSET 0x10100 84struct ahb_pciconf { 85 u32 vid_did; 86 u32 cmnd_sts; 87 u32 rev; 88 u32 cache_line; 89 u32 basead; 90}; 91 92/* PCI Configuration Registers for AHB-PCI Bridge Registers */ 93#define PCI_CONF_AHBPCI_OFFSET 0x10000 94struct ahbconf_pci_bridge { 95 u32 vid_did; /* 0x00 */ 96 u32 cmnd_sts; 97 u32 revid_cc; 98 u32 cls_lt_ht_bist; 99 u32 basead; /* 0x10 */ 100 u32 win1_basead; 101 u32 win2_basead; 102 u32 dummy0[5]; 103 u32 ssvdi_ssid; /* 0x2C */ 104 u32 dummy1[4]; 105 u32 intr_line_pin; 106}; 107 108/* AHB-PCI Bridge PCI Communication Registers */ 109#define AHBPCI_OFFSET 0x10800 110struct ahbcom_pci_bridge { 111 u32 pciahb_win1_ctr; /* 0x00 */ 112 u32 pciahb_win2_ctr; 113 u32 pciahb_dct_ctr; 114 u32 dummy0; 115 u32 ahbpci_win1_ctr; /* 0x10 */ 116 u32 ahbpci_win2_ctr; 117 u32 dummy1; 118 u32 ahbpci_dct_ctr; 119 u32 pci_int_enable; /* 0x20 */ 120 u32 pci_int_status; 121 u32 dummy2[2]; 122 u32 ahb_bus_ctr; /* 0x30 */ 123 u32 usbctr; 124 u32 dummy3[2]; 125 u32 pci_arbiter_ctr; /* 0x40 */ 126 u32 dummy4; 127 u32 pci_unit_rev; /* 0x48 */ 128}; 129 130struct rmobile_ehci_reg { 131 u32 hciversion; /* hciversion/caplength */ 132 u32 hcsparams; /* hcsparams */ 133 u32 hccparams; /* hccparams */ 134 u32 hcsp_portroute; /* hcsp_portroute */ 135 u32 usbcmd; /* usbcmd */ 136 u32 usbsts; /* usbsts */ 137 u32 usbintr; /* usbintr */ 138 u32 frindex; /* frindex */ 139 u32 ctrldssegment; /* ctrldssegment */ 140 u32 periodiclistbase; /* periodiclistbase */ 141 u32 asynclistaddr; /* asynclistaddr */ 142 u32 dummy[9]; 143 u32 configflag; /* configflag */ 144 u32 portsc; /* portsc */ 145}; 146 147#endif /* __EHCI_RMOBILE_H__ */ 148