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9#ifndef __ASM_ARM_ARCH_PWM_H_
10#define __ASM_ARM_ARCH_PWM_H_
11
12#define PRESCALER_0 (8 - 1)
13#define PRESCALER_1 (16 - 1)
14
15
16#define MUX_DIV_1 0
17#define MUX_DIV_2 1
18#define MUX_DIV_4 2
19#define MUX_DIV_8 3
20#define MUX_DIV_16 4
21
22#define MUX_DIV_SHIFT(x) (x * 4)
23
24#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
25
26#define TCON_START(x) (1 << TCON_OFFSET(x))
27#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
28#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
29#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
30#define TCON4_AUTO_RELOAD (1 << 22)
31
32#ifndef __ASSEMBLY__
33struct s5p_timer {
34 unsigned int tcfg0;
35 unsigned int tcfg1;
36 unsigned int tcon;
37 unsigned int tcntb0;
38 unsigned int tcmpb0;
39 unsigned int tcnto0;
40 unsigned int tcntb1;
41 unsigned int tcmpb1;
42 unsigned int tcnto1;
43 unsigned int tcntb2;
44 unsigned int tcmpb2;
45 unsigned int tcnto2;
46 unsigned int tcntb3;
47 unsigned int res1;
48 unsigned int tcnto3;
49 unsigned int tcntb4;
50 unsigned int tcnto4;
51 unsigned int tintcstat;
52};
53#endif
54
55#endif
56