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9#include <common.h>
10#include <linux/errno.h>
11#include <linux/io.h>
12#include <linux/sizes.h>
13#include <asm/processor.h>
14
15#include "../init.h"
16#include "ddrphy-init.h"
17#include "umc-regs.h"
18
19#define DRAM_CH_NR 2
20
21enum dram_freq {
22 DRAM_FREQ_1333M,
23 DRAM_FREQ_1600M,
24 DRAM_FREQ_NR,
25};
26
27enum dram_size {
28 DRAM_SZ_128M,
29 DRAM_SZ_256M,
30 DRAM_SZ_512M,
31 DRAM_SZ_NR,
32};
33
34static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
35static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
36static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
37static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
38static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
39 {0x00240512, 0x00350512, 0x00000000},
40 {0x002b0617, 0x003f0617, 0x00670617},
41};
42static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
43static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
44
45static int umc_get_rank(int ch)
46{
47 return ch;
48}
49
50static void umc_start_ssif(void __iomem *ssif_base)
51{
52 writel(0x00000000, ssif_base + 0x0000b004);
53 writel(0xffffffff, ssif_base + 0x0000c004);
54 writel(0x000fffcf, ssif_base + 0x0000c008);
55 writel(0x00000001, ssif_base + 0x0000b000);
56 writel(0x00000001, ssif_base + 0x0000c000);
57 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
58 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
59
60 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
61 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
62 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
63 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
64 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
65 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
66 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
67 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
68 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
69 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
70
71 writel(0x00000001, ssif_base + UMC_CPURST);
72 writel(0x00000001, ssif_base + UMC_IDSRST);
73 writel(0x00000001, ssif_base + UMC_IXMRST);
74 writel(0x00000001, ssif_base + UMC_MDMRST);
75 writel(0x00000001, ssif_base + UMC_MDDRST);
76 writel(0x00000001, ssif_base + UMC_SIORST);
77 writel(0x00000001, ssif_base + UMC_VIORST);
78 writel(0x00000001, ssif_base + UMC_FRCRST);
79 writel(0x00000001, ssif_base + UMC_RGLRST);
80 writel(0x00000001, ssif_base + UMC_AIORST);
81 writel(0x00000001, ssif_base + UMC_DMDRST);
82}
83
84static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
85 int freq, unsigned long size, bool ddr3plus)
86{
87 enum dram_freq freq_e;
88 enum dram_size size_e;
89
90 switch (freq) {
91 case 1333:
92 freq_e = DRAM_FREQ_1333M;
93 break;
94 case 1600:
95 freq_e = DRAM_FREQ_1600M;
96 break;
97 default:
98 pr_err("unsupported DRAM frequency %d MHz\n", freq);
99 return -EINVAL;
100 }
101
102 switch (size) {
103 case 0:
104 return 0;
105 case SZ_128M:
106 size_e = DRAM_SZ_128M;
107 break;
108 case SZ_256M:
109 size_e = DRAM_SZ_256M;
110 break;
111 case SZ_512M:
112 size_e = DRAM_SZ_512M;
113 break;
114 default:
115 pr_err("unsupported DRAM size 0x%08lx\n", size);
116 return -EINVAL;
117 }
118
119 writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
120 dc_base + UMC_CMDCTLA);
121 writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
122 dc_base + UMC_CMDCTLB);
123 writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
124 writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
125 writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
126 writel(0x04060806, dc_base + UMC_WDATACTL_D0);
127 writel(0x04a02000, dc_base + UMC_DATASET);
128 writel(0x00000000, ca_base + 0x2300);
129 writel(0x00400020, dc_base + UMC_DCCGCTL);
130 writel(0x00000003, dc_base + 0x7000);
131 writel(0x0000004f, dc_base + 0x8000);
132 writel(0x000000c3, dc_base + 0x8004);
133 writel(0x00000077, dc_base + 0x8008);
134 writel(0x0000003b, dc_base + UMC_DICGCTLA);
135 writel(0x020a0808, dc_base + UMC_DICGCTLB);
136 writel(0x00000004, dc_base + UMC_FLOWCTLG);
137 writel(0x80000201, ca_base + 0xc20);
138 writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
139 writel(0x00200000, dc_base + UMC_FLOWCTLB);
140 writel(0x00004444, dc_base + UMC_FLOWCTLC);
141 writel(0x200a0a00, dc_base + UMC_SPCSETB);
142 writel(0x00000000, dc_base + UMC_SPCSETD);
143 writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
144
145 return 0;
146}
147
148static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
149 int freq, unsigned long size, bool ddr3plus, int ch)
150{
151 void __iomem *phy_base = dc_base + 0x00001000;
152 int ret;
153
154 writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
155 while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
156 cpu_relax();
157
158 writel(0x00000101, dc_base + UMC_DIOCTLA);
159
160 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
161 if (ret)
162 return ret;
163
164 ddrphy_prepare_training(phy_base, umc_get_rank(ch));
165 ret = ddrphy_training(phy_base);
166 if (ret)
167 return ret;
168
169 return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
170}
171
172int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
173{
174 void __iomem *umc_base = (void __iomem *)0x5b800000;
175 void __iomem *ca_base = umc_base + 0x00001000;
176 void __iomem *dc_base = umc_base + 0x00400000;
177 void __iomem *ssif_base = umc_base;
178 int ch, ret;
179
180 for (ch = 0; ch < DRAM_CH_NR; ch++) {
181 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
182 bd->dram_ch[ch].size,
183 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
184 if (ret) {
185 pr_err("failed to initialize UMC ch%d\n", ch);
186 return ret;
187 }
188
189 ca_base += 0x00001000;
190 dc_base += 0x00200000;
191 }
192
193 umc_start_ssif(ssif_base);
194
195 return 0;
196}
197
