LXR uboot/arch/arm/mach-zynq/clk.c

   1/*
   2 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   3 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7#include <clk.h>
   8#include <common.h>
   9#include <dm.h>
  10#include <asm/arch/clk.h>
  11
  12DECLARE_GLOBAL_DATA_PTR;
  13
  14static const char * const clk_names[clk_max] = {
  15        "armpll", "ddrpll", "iopll",
  16        "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  17        "ddr2x", "ddr3x", "dci",
  18        "lqspi", "smc", "pcap", "gem0", "gem1",
  19        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  20        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  21        "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  22        "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  23        "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  24        "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  25        "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  26};
  27
  28/**
  29 * set_cpu_clk_info() - Setup clock information
  30 *
  31 * This function is called from common code after relocation and sets up the
  32 * clock information.
  33 */
  34int set_cpu_clk_info(void)
  35{
  36        struct clk clk;
  37        struct udevice *dev;
  38        ulong rate;
  39        int i, ret;
  40
  41        ret = uclass_get_device_by_driver(UCLASS_CLK,
  42                DM_GET_DRIVER(zynq_clk), &dev);
  43        if (ret)
  44                return ret;
  45
  46        for (i = 0; i < 2; i++) {
  47                clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  48                ret = clk_request(dev, &clk);
  49                if (ret < 0)
  50                        return ret;
  51
  52                rate = clk_get_rate(&clk) / 1000000;
  53                if (i)
  54                        gd->bd->bi_ddr_freq = rate;
  55                else
  56                        gd->bd->bi_arm_freq = rate;
  57
  58                clk_free(&clk);
  59        }
  60        gd->bd->bi_dsp_freq = 0;
  61
  62        return 0;
  63}
  64
  65/**
  66 * soc_clk_dump() - Print clock frequencies
  67 * Returns zero on success
  68 *
  69 * Implementation for the clk dump command.
  70 */
  71int soc_clk_dump(void)
  72{
  73        struct udevice *dev;
  74        int i, ret;
  75
  76        ret = uclass_get_device_by_driver(UCLASS_CLK,
  77                DM_GET_DRIVER(zynq_clk), &dev);
  78        if (ret)
  79                return ret;
  80
  81        printf("clk\t\tfrequency\n");
  82        for (i = 0; i < clk_max; i++) {
  83                const char *name = clk_names[i];
  84                if (name) {
  85                        struct clk clk;
  86                        unsigned long rate;
  87
  88                        clk.id = i;
  89                        ret = clk_request(dev, &clk);
  90                        if (ret < 0)
  91                                return ret;
  92
  93                        rate = clk_get_rate(&clk);
  94
  95                        clk_free(&clk);
  96
  97                        if (rate == (unsigned long)-ENOSYS)
  98                                printf("%10s%20s\n", name, "unknown");
  99                        else
 100                                printf("%10s%20lu\n", name, rate);
 101                }
 102        }
 103
 104        return 0;
 105}
 106