LXR uboot/arch/m68k/cpu/mcf52x2/cpu.c

   1/*
   2 * (C) Copyright 2003
   3 * Josef Baumgartner <josef.baumgartner@telex.de>
   4 *
   5 * MCF5282 additionals
   6 * (C) Copyright 2005
   7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8 *
   9 * MCF5275 additions
  10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  11 *
  12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17#include <common.h>
  18#include <watchdog.h>
  19#include <command.h>
  20#include <asm/immap.h>
  21#include <asm/io.h>
  22#include <netdev.h>
  23#include "cpu.h"
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27#ifdef  CONFIG_M5208
  28int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  29{
  30        rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  31
  32        udelay(1000);
  33
  34        out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  35
  36        /* we don't return! */
  37        return 0;
  38};
  39
  40int checkcpu(void)
  41{
  42        char buf1[32], buf2[32];
  43
  44        printf("CPU:   Freescale Coldfire MCF5208\n"
  45               "       CPU CLK %s MHz BUS CLK %s MHz\n",
  46               strmhz(buf1, gd->cpu_clk),
  47               strmhz(buf2, gd->bus_clk));
  48        return 0;
  49};
  50
  51#if defined(CONFIG_WATCHDOG)
  52/* Called by macro WATCHDOG_RESET */
  53void watchdog_reset(void)
  54{
  55        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  56
  57        out_be16(&wdt->sr, 0x5555);
  58        out_be16(&wdt->sr, 0xaaaa);
  59}
  60
  61int watchdog_disable(void)
  62{
  63        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  64
  65        /* reset watchdog counter */
  66        out_be16(&wdt->sr, 0x5555);
  67        out_be16(&wdt->sr, 0xaaaa);
  68        /* disable watchdog timer */
  69        out_be16(&wdt->cr, 0);
  70
  71        puts("WATCHDOG:disabled\n");
  72        return (0);
  73}
  74
  75int watchdog_init(void)
  76{
  77        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  78
  79        /* disable watchdog */
  80        out_be16(&wdt->cr, 0);
  81
  82        /* set timeout and enable watchdog */
  83        out_be16(&wdt->mr,
  84                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  85
  86        /* reset watchdog counter */
  87        out_be16(&wdt->sr, 0x5555);
  88        out_be16(&wdt->sr, 0xaaaa);
  89
  90        puts("WATCHDOG:enabled\n");
  91        return (0);
  92}
  93#endif                          /* #ifdef CONFIG_WATCHDOG */
  94#endif                          /* #ifdef CONFIG_M5208 */
  95
  96#ifdef  CONFIG_M5271
  97/*
  98 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
  99 * determine which one we are running on, based on the Chip Identification
 100 * Register (CIR).
 101 */
 102int checkcpu(void)
 103{
 104        char buf[32];
 105        unsigned short cir;     /* Chip Identification Register */
 106        unsigned short pin;     /* Part identification number */
 107        unsigned char prn;      /* Part revision number */
 108        char *cpu_model;
 109
 110        cir = mbar_readShort(MCF_CCM_CIR);
 111        pin = cir >> MCF_CCM_CIR_PIN_LEN;
 112        prn = cir & MCF_CCM_CIR_PRN_MASK;
 113
 114        switch (pin) {
 115        case MCF_CCM_CIR_PIN_MCF5270:
 116                cpu_model = "5270";
 117                break;
 118        case MCF_CCM_CIR_PIN_MCF5271:
 119                cpu_model = "5271";
 120                break;
 121        default:
 122                cpu_model = NULL;
 123                break;
 124        }
 125
 126        if (cpu_model)
 127                printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
 128                       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
 129        else
 130                printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
 131                       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
 132                       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
 133
 134        return 0;
 135}
 136
 137int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 138{
 139        /* Call the board specific reset actions first. */
 140        if(board_reset) {
 141                board_reset();
 142        }
 143
 144        mbar_writeByte(MCF_RCM_RCR,
 145                       MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
 146        return 0;
 147};
 148
 149#if defined(CONFIG_WATCHDOG)
 150void watchdog_reset(void)
 151{
 152        mbar_writeShort(MCF_WTM_WSR, 0x5555);
 153        mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
 154}
 155
 156int watchdog_disable(void)
 157{
 158        mbar_writeShort(MCF_WTM_WCR, 0);
 159        return (0);
 160}
 161
 162int watchdog_init(void)
 163{
 164        mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
 165        return (0);
 166}
 167#endif                          /* #ifdef CONFIG_WATCHDOG */
 168
 169#endif
 170
 171#ifdef  CONFIG_M5272
 172int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 173{
 174        wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 175
 176        out_be16(&wdp->wdog_wrrr, 0);
 177        udelay(1000);
 178
 179        /* enable watchdog, set timeout to 0 and wait */
 180        out_be16(&wdp->wdog_wrrr, 1);
 181        while (1) ;
 182
 183        /* we don't return! */
 184        return 0;
 185};
 186
 187int checkcpu(void)
 188{
 189        sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 190        uchar msk;
 191        char *suf;
 192
 193        puts("CPU:   ");
 194        msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
 195        switch (msk) {
 196        case 0x2:
 197                suf = "1K75N";
 198                break;
 199        case 0x4:
 200                suf = "3K75N";
 201                break;
 202        default:
 203                suf = NULL;
 204                printf("Freescale MCF5272 (Mask:%01x)\n", msk);
 205                break;
 206        }
 207
 208        if (suf)
 209                printf("Freescale MCF5272 %s\n", suf);
 210        return 0;
 211};
 212
 213#if defined(CONFIG_WATCHDOG)
 214/* Called by macro WATCHDOG_RESET */
 215void watchdog_reset(void)
 216{
 217        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 218
 219        out_be16(&wdt->wdog_wcr, 0);
 220}
 221
 222int watchdog_disable(void)
 223{
 224        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 225
 226        /* reset watchdog counter */
 227        out_be16(&wdt->wdog_wcr, 0);
 228        /* disable watchdog interrupt */
 229        out_be16(&wdt->wdog_wirr, 0);
 230        /* disable watchdog timer */
 231        out_be16(&wdt->wdog_wrrr, 0);
 232
 233        puts("WATCHDOG:disabled\n");
 234        return (0);
 235}
 236
 237int watchdog_init(void)
 238{
 239        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 240
 241        /* disable watchdog interrupt */
 242        out_be16(&wdt->wdog_wirr, 0);
 243
 244        /* set timeout and enable watchdog */
 245        out_be16(&wdt->wdog_wrrr,
 246                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 247
 248        /* reset watchdog counter */
 249        out_be16(&wdt->wdog_wcr, 0);
 250
 251        puts("WATCHDOG:enabled\n");
 252        return (0);
 253}
 254#endif                          /* #ifdef CONFIG_WATCHDOG */
 255
 256#endif                          /* #ifdef CONFIG_M5272 */
 257
 258#ifdef  CONFIG_M5275
 259int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 260{
 261        rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 262
 263        udelay(1000);
 264
 265        out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 266
 267        /* we don't return! */
 268        return 0;
 269};
 270
 271int checkcpu(void)
 272{
 273        char buf[32];
 274
 275        printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
 276                        strmhz(buf, CONFIG_SYS_CLK));
 277        return 0;
 278};
 279
 280
 281#if defined(CONFIG_WATCHDOG)
 282/* Called by macro WATCHDOG_RESET */
 283void watchdog_reset(void)
 284{
 285        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 286
 287        out_be16(&wdt->wsr, 0x5555);
 288        out_be16(&wdt->wsr, 0xaaaa);
 289}
 290
 291int watchdog_disable(void)
 292{
 293        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 294
 295        /* reset watchdog counter */
 296        out_be16(&wdt->wsr, 0x5555);
 297        out_be16(&wdt->wsr, 0xaaaa);
 298
 299        /* disable watchdog timer */
 300        out_be16(&wdt->wcr, 0);
 301
 302        puts("WATCHDOG:disabled\n");
 303        return (0);
 304}
 305
 306int watchdog_init(void)
 307{
 308        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 309
 310        /* disable watchdog */
 311        out_be16(&wdt->wcr, 0);
 312
 313        /* set timeout and enable watchdog */
 314        out_be16(&wdt->wmr,
 315                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 316
 317        /* reset watchdog counter */
 318        out_be16(&wdt->wsr, 0x5555);
 319        out_be16(&wdt->wsr, 0xaaaa);
 320
 321        puts("WATCHDOG:enabled\n");
 322        return (0);
 323}
 324#endif                          /* #ifdef CONFIG_WATCHDOG */
 325
 326#endif                          /* #ifdef CONFIG_M5275 */
 327
 328#ifdef  CONFIG_M5282
 329int checkcpu(void)
 330{
 331        unsigned char resetsource = MCFRESET_RSR;
 332
 333        printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
 334               MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
 335        printf("Reset:%s%s%s%s%s%s%s\n",
 336               (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
 337               (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
 338               (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
 339               (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
 340               (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
 341               (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
 342               (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
 343        return 0;
 344}
 345
 346int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 347{
 348        MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 349        return 0;
 350};
 351#endif
 352
 353#ifdef CONFIG_M5249
 354int checkcpu(void)
 355{
 356        char buf[32];
 357
 358        printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
 359               strmhz(buf, CONFIG_SYS_CLK));
 360        return 0;
 361}
 362
 363int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 364{
 365        /* enable watchdog, set timeout to 0 and wait */
 366        mbar_writeByte(MCFSIM_SYPCR, 0xc0);
 367        while (1) ;
 368
 369        /* we don't return! */
 370        return 0;
 371};
 372#endif
 373
 374#ifdef CONFIG_M5253
 375int checkcpu(void)
 376{
 377        char buf[32];
 378
 379        unsigned char resetsource = mbar_readLong(SIM_RSR);
 380        printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
 381               strmhz(buf, CONFIG_SYS_CLK));
 382
 383        if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 384                printf("Reset:%s%s\n",
 385                       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
 386                       : "",
 387                       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
 388                       "");
 389        }
 390        return 0;
 391}
 392
 393int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 394{
 395        /* enable watchdog, set timeout to 0 and wait */
 396        mbar_writeByte(SIM_SYPCR, 0xc0);
 397        while (1) ;
 398
 399        /* we don't return! */
 400        return 0;
 401};
 402#endif
 403
 404#if defined(CONFIG_MCFFEC)
 405/* Default initializations for MCFFEC controllers.  To override,
 406 * create a board-specific function called:
 407 *      int board_eth_init(bd_t *bis)
 408 */
 409
 410int cpu_eth_init(bd_t *bis)
 411{
 412        return mcffec_initialize(bis);
 413}
 414#endif
 415