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9#ifndef _BRASWELL_GPIO_H_
10#define _BRASWELL_GPIO_H_
11
12#include <asm/arch/iomap.h>
13
14enum mode_list {
15 M0,
16 M1,
17 M2,
18 M3,
19 M4,
20 M5,
21 M6,
22 M7,
23 M8,
24 M9,
25 M10,
26 M11,
27 M12,
28 M13,
29};
30
31enum int_select {
32 L0,
33 L1,
34 L2,
35 L3,
36 L4,
37 L5,
38 L6,
39 L7,
40 L8,
41 L9,
42 L10,
43 L11,
44 L12,
45 L13,
46 L14,
47 L15,
48};
49
50enum gpio_en {
51 NATIVE = 0xff,
52 GPIO = 0,
53 GPO = 1,
54 GPI = 2,
55 HI_Z = 3,
56 NA_GPO = 0,
57};
58
59enum gpio_state {
60 LOW,
61 HIGH,
62};
63
64enum en_dis {
65 DISABLE,
66 ENABLE,
67};
68
69enum int_type {
70 INT_DIS,
71 TRIG_EDGE_LOW,
72 TRIG_EDGE_HIGH,
73 TRIG_EDGE_BOTH,
74 TRIG_LEVEL,
75};
76
77enum mask {
78 MASKABLE,
79 NON_MASKABLE,
80};
81
82enum glitch_cfg {
83 GLITCH_DISABLE,
84 EN_EDGE_DETECT,
85 EN_RX_DATA,
86 EN_EDGE_RX_DATA,
87};
88
89enum inv_rx_tx {
90 NO_INVERSION = 0,
91 INV_RX_ENABLE = 1,
92 INV_TX_ENABLE = 2,
93 INV_RX_TX_ENABLE = 3,
94 INV_RX_DATA = 4,
95 INV_TX_DATA = 8,
96};
97
98enum voltage {
99 VOLT_3_3,
100 VOLT_1_8,
101};
102
103enum hs_mode {
104 DISABLE_HS,
105 ENABLE_HS,
106};
107
108enum odt_up_dn {
109 PULL_UP,
110 PULL_DOWN,
111};
112
113enum odt_en {
114 DISABLE_OD,
115 ENABLE_OD,
116};
117
118enum pull_type {
119 P_NONE = 0,
120 P_20K_L = 1,
121 P_5K_L = 2,
122 P_1K_L = 4,
123 P_20K_H = 9,
124 P_5K_H = 10,
125 P_1K_H = 12
126};
127
128enum bit {
129 ONE_BIT = 1,
130 TWO_BIT = 3,
131 THREE_BIT = 7,
132 FOUR_BIT = 15,
133 FIVE_BIT = 31,
134 SIX_BIT = 63,
135 SEVEN_BIT = 127,
136 EIGHT_BIT = 255
137};
138
139enum gpe_config {
140 GPE,
141 SMI,
142 SCI,
143};
144
145enum community {
146 SOUTHWEST = 0x0000,
147 NORTH = 0x8000,
148 EAST = 0x10000,
149 SOUTHEAST = 0x18000,
150 VIRTUAL = 0x20000,
151};
152
153#define NA 0xff
154#define TERMINATOR 0xffffffff
155
156#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
157 odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
158 .confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
159 (((hysctl) != NA) ? hysctl << 24 : 0) | \
160 (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
161 (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
162 (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
163 (((odt_en) != NA) ? odt_en << 17 : 0) | \
164 (curr_src_str)), \
165 .confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
166 (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
167 (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
168 (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
169 (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
170 (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
171 (THREE_BIT)), \
172 .misc = ((rcomp == ENABLE) ? 1 : 0) , \
173 .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
174 ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
175 (0x80 * family_no) + 0x1080) : 0) , \
176 .name = 0 \
177}
178
179#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
180 gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
181 int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
182 mmio_offset, community_offset) { \
183 .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
184 (((glitch) != NA) ? (glitch << 26) : 0) | \
185 (((term) != NA) ? (term << 20) : 0) | \
186 (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
187 ((mode << 16))) | \
188 (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
189 (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
190 (((gpio_state) == HIGH) ? 2 : 0)), \
191 .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
192 (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
193 (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
194 (FIVE_BIT << 15) | \
195 (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
196 (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
197 (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
198 .confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
199 (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
200 (((open_drain) != NA) ? open_drain << 3 : 0) | \
201 (((int_type) != NA) ? int_type : 0)), \
202 .confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
203 (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
204 (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
205 (((int_type) != NA) ? THREE_BIT : 0)), \
206 .community = community_offset, \
207 .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
208 ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
209 community_offset + mmio_offset) : 0), \
210 .name = 0, \
211 .misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
212 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
213 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
214 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
215}
216
217#endif
218
