/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 *
 * Based on: gw_ventana_spl.c which is:
 * Copyright (C) 2014 Gateworks Corporation
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>

#include "platinum.h"

DECLARE_GLOBAL_DATA_PTR;

#undef RTT_NOM_120OHM   /* use 120ohm Rtt_nom vs 60ohm (lower power) */

/* Configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
        /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
        .dram_sdclk_0 = 0x00020030,
        .dram_sdclk_1 = 0x00020030,
        .dram_cas = 0x00020030,
        .dram_ras = 0x00020030,
        .dram_reset = 0x00020030,
        /* SDCKE[0:1]: 100k pull-up */
        .dram_sdcke0 = 0x00003000,
        .dram_sdcke1 = 0x00003000,
        /* SDBA2: pull-up disabled */
        .dram_sdba2 = 0x00000000,
        /* SDODT[0:1]: 100k pull-up, 40 ohm */
        .dram_sdodt0 = 0x00003030,
        .dram_sdodt1 = 0x00003030,
        /* SDQS[0:7]: Differential input, 40 ohm */
        .dram_sdqs0 = 0x00000030,
        .dram_sdqs1 = 0x00000030,
        .dram_sdqs2 = 0x00000030,
        .dram_sdqs3 = 0x00000030,
        .dram_sdqs4 = 0x00000030,
        .dram_sdqs5 = 0x00000030,
        .dram_sdqs6 = 0x00000030,
        .dram_sdqs7 = 0x00000030,
        /* DQM[0:7]: Differential input, 40 ohm */
        .dram_dqm0 = 0x00020030,
        .dram_dqm1 = 0x00020030,
        .dram_dqm2 = 0x00020030,
        .dram_dqm3 = 0x00020030,
        .dram_dqm4 = 0x00020030,
        .dram_dqm5 = 0x00020030,
        .dram_dqm6 = 0x00020030,
        .dram_dqm7 = 0x00020030,
};

/* Configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
        /* DDR3 */
        .grp_ddr_type = 0x000c0000,
        .grp_ddrmode_ctl = 0x00020000,
        /* disable DDR pullups */
        .grp_ddrpke = 0x00000000,
        /* ADDR[00:16], SDBA[0:1]: 40 ohm */
        .grp_addds = 0x00000030,
        /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
        .grp_ctlds = 0x00000030,
        /* DATA[00:63]: Differential input, 40 ohm */
        .grp_ddrmode = 0x00020000,
        .grp_b0ds = 0x00000030,
        .grp_b1ds = 0x00000030,
        .grp_b2ds = 0x00000030,
        .grp_b3ds = 0x00000030,
        .grp_b4ds = 0x00000030,
        .grp_b5ds = 0x00000030,
        .grp_b6ds = 0x00000030,
        .grp_b7ds = 0x00000030,
};

/* MT41J128M16JT-125 */
static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
        .mem_speed = 1600,
        .density = 2,
        .width = 16,
        .banks = 8,
        .rowaddr = 14,
        .coladdr = 10,
        .pagesz = 2,
        .trcd = 1375,
        .trcmin = 4875,
        .trasmin = 3500,
};

static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
        /* Write leveling calibration determine */
        .p0_mpwldectrl0 = 0x001f001f,
        .p0_mpwldectrl1 = 0x001f001f,
        .p1_mpwldectrl0 = 0x00440044,
        .p1_mpwldectrl1 = 0x00440044,
        /* Read DQS Gating calibration */
        .p0_mpdgctrl0 = 0x434b0350,
        .p0_mpdgctrl1 = 0x034c0359,
        .p1_mpdgctrl0 = 0x434b0350,
        .p1_mpdgctrl1 = 0x03650348,
        /* Read Calibration: DQS delay relative to DQ read access */
        .p0_mprddlctl = 0x4436383b,
        .p1_mprddlctl = 0x39393341,
        /* Write Calibration: DQ/DM delay relative to DQS write access */
        .p0_mpwrdlctl = 0x35373933,
        .p1_mpwrdlctl = 0x48254a36,
};

static void spl_dram_init(int width)
{
        struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
        struct mx6_ddr_sysinfo sysinfo = {
                /* width of data bus:0=16,1=32,2=64 */
                .dsize = width / 32,
                /* config for full 4GB range so that get_mem_size() works */
                .cs_density = 32, /* 32Gb per CS */
                /* single chip select */
                .ncs = 1,
                .cs1_mirror = 1,
                .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
                .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
#else
                .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
#endif
                .walat = 0,     /* Write additional latency */
                .ralat = 5,     /* Read additional latency */
                .mif3_mode = 3, /* Command prediction working mode */
                .bi_on = 1,     /* Bank interleaving enabled */
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
                .ddr_type = DDR_TYPE_DDR3,
                .refsel = 1,            /* Refresh cycles at 32KHz */
                .refr = 7,              /* 8 refresh commands per refresh cycle */
        };

        mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
        mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}

/*
 * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
        /* Setup AIPS and disable watchdog */
        arch_cpu_init();

        ccgr_init();
        gpr_init();

        /* UART iomux */
        board_early_init_f();

        /* Setup GP timer */
        timer_init();

        /* UART clocks enabled and gd valid - init serial console */
        preloader_console_init();

        /* Init DDR with 32bit width */
        spl_dram_init(32);

        /* Clear the BSS */
        memset(__bss_start, 0, __bss_end - __bss_start);

        /*
         * Setup enet related MUXing early to give the PHY
         * some time to wake-up from reset
         */
        platinum_setup_enet();

        /* load/boot image from boot device */
        board_init_r(NULL, 0);
}