LXR uboot/board/cssi/MCR3000/MCR3000.c

   1/*
   2 * Copyright (C) 2010-2017 CS Systemes d'Information
   3 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   4 * Christophe Leroy <christophe.leroy@c-s.fr>
   5 *
   6 * Board specific routines for the MCR3000 board
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#include <common.h>
  12#include <hwconfig.h>
  13#include <mpc8xx.h>
  14#include <fdt_support.h>
  15#include <asm/io.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19static const uint cs1_dram_table_66[] = {
  20        /* DRAM - single read. (offset 0 in upm RAM) */
  21        0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  22        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  23
  24        /* DRAM - burst read. (offset 8 in upm RAM) */
  25        0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  26        0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  27        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  28        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  29
  30        /* DRAM - single write. (offset 18 in upm RAM) */
  31        0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  32        0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  33
  34        /* DRAM - burst write. (offset 20 in upm RAM) */
  35        0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  36        0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  37        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  38        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  39
  40        /* refresh  (offset 30 in upm RAM) */
  41        0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  42        0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  43
  44        /* init */
  45        0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  46
  47        /* exception. (offset 3c in upm RAM) */
  48        0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  49};
  50
  51int ft_board_setup(void *blob, bd_t *bd)
  52{
  53        const char *sync = "receive";
  54
  55        ft_cpu_setup(blob, bd);
  56
  57        /* BRG */
  58        do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  59                             bd->bi_busfreq, 1);
  60
  61        /* MAC addr */
  62        fdt_fixup_ethernet(blob);
  63
  64        /* Bus Frequency for CPM */
  65        do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  66
  67        /* E1 interface - Set data rate */
  68        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  69
  70        /* E1 interface - Set channel phase to 0 */
  71        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  72
  73        /* E1 interface - rising edge sync pulse transmit */
  74        do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  75                         sync, strlen(sync), 1);
  76
  77        return 0;
  78}
  79
  80int checkboard(void)
  81{
  82        serial_puts("BOARD: MCR3000 CSSI\n");
  83
  84        return 0;
  85}
  86
  87int dram_init(void)
  88{
  89        immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  90        memctl8xx_t __iomem *memctl = &immap->im_memctl;
  91
  92        printf("UPMA init for SDRAM (CAS latency 2), ");
  93        printf("init address 0x%08x, size ", (int)dram_init);
  94        /* Configure UPMA for cs1 */
  95        upmconfig(UPMA, (uint *)cs1_dram_table_66,
  96                  sizeof(cs1_dram_table_66) / sizeof(uint));
  97        udelay(10);
  98        out_be16(&memctl->memc_mptpr, 0x0200);
  99        out_be32(&memctl->memc_mamr, 0x14904000);
 100        udelay(10);
 101        out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 102        out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 103        udelay(10);
 104        out_be32(&memctl->memc_mcr, 0x80002830);
 105        out_be32(&memctl->memc_mar, 0x00000088);
 106        out_be32(&memctl->memc_mcr, 0x80002038);
 107        udelay(200);
 108
 109        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 110                                    SDRAM_MAX_SIZE);
 111
 112        return 0;
 113}
 114
 115int misc_init_r(void)
 116{
 117        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 118        iop8xx_t __iomem *iop = &immr->im_ioport;
 119
 120        /* Set port C13 as GPIO (BTN_ACQ_AL) */
 121        clrbits_be16(&iop->iop_pcpar, 0x4);
 122        clrbits_be16(&iop->iop_pcdir, 0x4);
 123
 124        /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 125        if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 126                env_set("bootdelay", "60");
 127
 128        return 0;
 129}
 130
 131int board_early_init_f(void)
 132{
 133        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 134
 135        /*
 136         * Erase FPGA(s) for reboot
 137         */
 138        clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 139        setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 140        udelay(1);                              /* Wait more than 300ns */
 141        setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 142
 143        return 0;
 144}
 145