LXR uboot/board/freescale/c29xpcie/ddr.c

   1/*
   2 * Copyright 2013 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <asm/fsl_law.h>
  10#include <fsl_ddr_sdram.h>
  11#include <fsl_ddr_dimm_params.h>
  12
  13#include "cpld.h"
  14
  15#define C29XPCIE_HARDWARE_REVA  0x40
  16/*
  17 * Micron MT41J128M16HA-15E
  18 * */
  19dimm_params_t ddr_raw_timing = {
  20        .n_ranks = 1,
  21        .rank_density = 536870912u,
  22        .capacity = 536870912u,
  23        .primary_sdram_width = 32,
  24        .ec_sdram_width = 8,
  25        .registered_dimm = 0,
  26        .mirrored_dimm = 0,
  27        .n_row_addr = 14,
  28        .n_col_addr = 10,
  29        .n_banks_per_sdram_device = 8,
  30        .edc_config = 2,
  31        .burst_lengths_bitmask = 0x0c,
  32
  33        .tckmin_x_ps = 1650,
  34        .caslat_x = 0x7e << 4,  /* 5,6,7,8,9,10 */
  35        .taa_ps = 14050,
  36        .twr_ps = 15000,
  37        .trcd_ps = 13500,
  38        .trrd_ps = 75000,
  39        .trp_ps = 13500,
  40        .tras_ps = 40000,
  41        .trc_ps = 49500,
  42        .trfc_ps = 160000,
  43        .twtr_ps = 75000,
  44        .trtp_ps = 75000,
  45        .refresh_rate_ps = 7800000,
  46        .tfaw_ps = 30000,
  47};
  48
  49int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  50                unsigned int controller_number,
  51                unsigned int dimm_number)
  52{
  53        const char dimm_model[] = "Fixed DDR on board";
  54
  55        if ((controller_number == 0) && (dimm_number == 0)) {
  56                memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  57                memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  58                memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  59        }
  60
  61        return 0;
  62}
  63
  64void fsl_ddr_board_options(memctl_options_t *popts,
  65                                dimm_params_t *pdimm,
  66                                unsigned int ctrl_num)
  67{
  68        struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  69        int i;
  70
  71        popts->clk_adjust = 4;
  72        popts->cpo_override = 0x1f;
  73        popts->write_data_delay = 4;
  74        popts->half_strength_driver_enable = 1;
  75        popts->bstopre = 0x3cf;
  76        popts->quad_rank_present = 1;
  77        popts->rtt_override = 1;
  78        popts->rtt_override_value = 1;
  79        popts->dynamic_power = 1;
  80        /* Write leveling override */
  81        popts->wrlvl_en = 1;
  82        popts->wrlvl_override = 1;
  83        popts->wrlvl_sample = 0xf;
  84        popts->wrlvl_start = 0x4;
  85        popts->trwt_override = 1;
  86        popts->trwt = 0;
  87
  88        if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
  89                popts->ecc_mode = 0;
  90
  91        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  92                popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  93                popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  94        }
  95}
  96
  97void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  98{
  99        int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
 100                                sizeof(generic_spd_eeprom_t));
 101
 102        if (ret) {
 103                printf("DDR: failed to read SPD from address %u\n",
 104                                i2c_address);
 105                memset(spd, 0, sizeof(generic_spd_eeprom_t));
 106        }
 107}
 108