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7#include <common.h>
8#include <asm/mmu.h>
9#include <asm/immap_85xx.h>
10#include <asm/processor.h>
11#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
13#include <asm/io.h>
14#include <asm/fsl_law.h>
15
16#ifdef CONFIG_SYS_DDR_RAW_TIMING
17#if defined(CONFIG_P1020RDB_PROTO) || \
18 defined(CONFIG_TARGET_P1021RDB) || \
19 defined(CONFIG_TARGET_P1020UTM)
20
21dimm_params_t ddr_raw_timing = {
22 .n_ranks = 1,
23 .rank_density = 1073741824u,
24 .capacity = 1073741824u,
25 .primary_sdram_width = 32,
26 .ec_sdram_width = 0,
27 .registered_dimm = 0,
28 .mirrored_dimm = 0,
29 .n_row_addr = 15,
30 .n_col_addr = 10,
31 .n_banks_per_sdram_device = 8,
32 .edc_config = 0,
33 .burst_lengths_bitmask = 0x0c,
34
35 .tckmin_x_ps = 1870,
36 .caslat_x = 0x1e << 4,
37 .taa_ps = 13125,
38 .twr_ps = 15000,
39 .trcd_ps = 13125,
40 .trrd_ps = 7500,
41 .trp_ps = 13125,
42 .tras_ps = 37500,
43 .trc_ps = 50625,
44 .trfc_ps = 160000,
45 .twtr_ps = 7500,
46 .trtp_ps = 7500,
47 .refresh_rate_ps = 7800000,
48 .tfaw_ps = 37500,
49};
50#elif defined(CONFIG_TARGET_P2020RDB)
51
52dimm_params_t ddr_raw_timing = {
53 .n_ranks = 1,
54 .rank_density = 1073741824u,
55 .capacity = 1073741824u,
56 .primary_sdram_width = 64,
57 .ec_sdram_width = 0,
58 .registered_dimm = 0,
59 .mirrored_dimm = 0,
60 .n_row_addr = 14,
61 .n_col_addr = 10,
62 .n_banks_per_sdram_device = 8,
63 .edc_config = 0,
64 .burst_lengths_bitmask = 0x0c,
65
66 .tckmin_x_ps = 1500,
67 .caslat_x = 0x7e << 4,
68 .taa_ps = 13500,
69 .twr_ps = 15000,
70 .trcd_ps = 13500,
71 .trrd_ps = 6000,
72 .trp_ps = 13500,
73 .tras_ps = 36000,
74 .trc_ps = 49500,
75 .trfc_ps = 160000,
76 .twtr_ps = 7500,
77 .trtp_ps = 7500,
78 .refresh_rate_ps = 7800000,
79 .tfaw_ps = 30000,
80};
81#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
82
83dimm_params_t ddr_raw_timing = {
84 .n_ranks = 2,
85 .rank_density = 1073741824u,
86 .capacity = 2147483648u,
87 .primary_sdram_width = 32,
88 .ec_sdram_width = 0,
89 .registered_dimm = 0,
90 .mirrored_dimm = 0,
91 .n_row_addr = 15,
92 .n_col_addr = 10,
93 .n_banks_per_sdram_device = 8,
94 .edc_config = 0,
95 .burst_lengths_bitmask = 0x0c,
96
97 .tckmin_x_ps = 1870,
98 .caslat_x = 0x1e << 4,
99 .taa_ps = 13125,
100 .twr_ps = 15000,
101 .trcd_ps = 13125,
102 .trrd_ps = 7500,
103 .trp_ps = 13125,
104 .tras_ps = 37500,
105 .trc_ps = 50625,
106 .trfc_ps = 160000,
107 .twtr_ps = 7500,
108 .trtp_ps = 7500,
109 .refresh_rate_ps = 7800000,
110 .tfaw_ps = 37500,
111};
112#elif defined(CONFIG_TARGET_P1020RDB_PC)
113
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117
118
119
120dimm_params_t ddr_raw_timing = {
121 .n_ranks = 1,
122 .rank_density = 1073741824u,
123 .capacity = 1073741824u,
124 .primary_sdram_width = 32,
125 .ec_sdram_width = 0,
126 .registered_dimm = 0,
127 .mirrored_dimm = 0,
128 .n_row_addr = 15,
129 .n_col_addr = 10,
130 .n_banks_per_sdram_device = 8,
131 .edc_config = 0,
132 .burst_lengths_bitmask = 0x0c,
133
134 .tckmin_x_ps = 1875,
135 .caslat_x = 0x1e << 4,
136 .taa_ps = 13125,
137 .twr_ps = 15000,
138 .trcd_ps = 13125,
139 .trrd_ps = 7500,
140 .trp_ps = 13125,
141 .tras_ps = 37500,
142 .trc_ps = 50625,
143 .trfc_ps = 160000,
144 .twtr_ps = 7500,
145 .trtp_ps = 7500,
146 .refresh_rate_ps = 7800000,
147 .tfaw_ps = 37500,
148};
149#elif defined(CONFIG_TARGET_P1024RDB) || \
150 defined(CONFIG_TARGET_P1025RDB)
151
152
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155
156
157
158dimm_params_t ddr_raw_timing = {
159 .n_ranks = 1,
160 .rank_density = 1073741824u,
161 .capacity = 1073741824u,
162 .primary_sdram_width = 32,
163 .ec_sdram_width = 0,
164 .registered_dimm = 0,
165 .mirrored_dimm = 0,
166 .n_row_addr = 15,
167 .n_col_addr = 10,
168 .n_banks_per_sdram_device = 8,
169 .edc_config = 0,
170 .burst_lengths_bitmask = 0x0c,
171
172 .tckmin_x_ps = 1500,
173 .caslat_x = 0x3e << 4,
174 .taa_ps = 13125,
175 .twr_ps = 15000,
176 .trcd_ps = 13125,
177 .trrd_ps = 6000,
178 .trp_ps = 13125,
179 .tras_ps = 36000,
180 .trc_ps = 49125,
181 .trfc_ps = 160000,
182 .twtr_ps = 7500,
183 .trtp_ps = 7500,
184 .refresh_rate_ps = 7800000,
185 .tfaw_ps = 30000,
186};
187#else
188#error Missing raw timing data for this board
189#endif
190
191int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
192 unsigned int controller_number,
193 unsigned int dimm_number)
194{
195 const char dimm_model[] = "Fixed DDR on board";
196
197 if ((controller_number == 0) && (dimm_number == 0)) {
198 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
199 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
200 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
201 }
202
203 return 0;
204}
205#endif
206
207#ifdef CONFIG_SYS_DDR_CS0_BNDS
208
209phys_size_t fixed_sdram(void)
210{
211 sys_info_t sysinfo;
212 char buf[32];
213 size_t ddr_size;
214 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
215 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
216 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
217 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
218#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
219 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
220 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
221 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
222#endif
223 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
224 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
225 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
226 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
227 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
228 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
229 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
230 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
231 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
232 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
233 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
234 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
235 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
236 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
237 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
238 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
239 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
240 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
241 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
242 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
243 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
244 };
245
246 get_sys_info(&sysinfo);
247 printf("Configuring DDR for %s MT/s data rate\n",
248 strmhz(buf, sysinfo.freq_ddrbus));
249
250 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
251
252 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
253
254 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
255 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
256 printf("ERROR setting Local Access Windows for DDR\n");
257 return 0;
258 };
259
260 return ddr_size;
261}
262#endif
263
264void fsl_ddr_board_options(memctl_options_t *popts,
265 dimm_params_t *pdimm,
266 unsigned int ctrl_num)
267{
268 int i;
269 popts->clk_adjust = 6;
270 popts->cpo_override = 0x1f;
271 popts->write_data_delay = 2;
272 popts->half_strength_driver_enable = 1;
273
274 popts->wrlvl_en = 1;
275 popts->wrlvl_override = 1;
276 popts->wrlvl_sample = 0xf;
277 popts->wrlvl_start = 0x8;
278 popts->trwt_override = 1;
279 popts->trwt = 0;
280
281 if (pdimm->primary_sdram_width == 64)
282 popts->data_bus_width = 0;
283 else if (pdimm->primary_sdram_width == 32)
284 popts->data_bus_width = 1;
285 else
286 printf("Error in DDR bus width configuration!\n");
287
288 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
289 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
290 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
291 }
292}
293
