1/* 2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 3 * 4 * Copyright (C) 2006 Micronas GmbH 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef _SCC_H 10#define _SCC_H 11 12#define DMA_READ 0 /* SCC read DMA */ 13#define DMA_WRITE 1 /* SCC write DMA */ 14 15#define DMA_LINEAR 0 /* DMA linear buffer access method */ 16#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */ 17 18#define DMA_START 0 /* DMA command - start DMA */ 19#define DMA_STOP 1 /* DMA command - stop DMA */ 20#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */ 21#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */ 22 23#define AGU_ACTIVE 0 /* enable AGU address calculation */ 24#define AGU_BYPASS 1 /* set AGU to bypass mode */ 25 26#define USE_NO_FH 0 /* order the DMA to not use FH */ 27#define USE_FH 1 /* order the DMA to work with FH*/ 28 29#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */ 30#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */ 31 32#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/ 33#define TO_DMA_CFG 2 /* takeover command for the DMA config*/ 34 35#define DMA_CMD_RESET 0 36#define DMA_CMD_SETUP 1 37#define DMA_CMD_START 2 38#define DMA_CMD_STOP 3 39 40#define DMA_STATE_RESET 0 41#define DMA_STATE_SETUP 1 42#define DMA_STATE_START 2 43#define DMA_STATE_ERROR 3 44 45#define SRMD 0 46#define STRM_D 1 47#define STRM_P 2 48 49/* 50 * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks) 51 */ 52#define RESET_TIME 2 /* cycle calc see in SCC_Reset */ 53 54struct scc_descriptor { 55 char *pu_name; /* PU identifier */ 56 char *scc_instance; /* SCC Name */ 57 u32 profile; /* SCC VCI_D profile */ 58 59 u32 base_address; /* base address of the SCC unit reg shell*/ 60 61 /* SCS Interconnect configuration */ 62 u32 p_scc_id; /* instance number of SCC unit */ 63 u32 p_mci_id; /* memory channel ID */ 64 65 /* DMA Registers configuration */ 66 u32 p_dma_channels_rd; /* Number of Read DMA channels */ 67 u32 p_dma_channels_wr; /* Number of Write DMA channels */ 68 69 u32 p_dma_packet_desc; /* Number of packet descriptors */ 70 u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */ 71 72 int use_fh; /* the flag tells if SCC uses an FH */ 73 74 int p_si2ocp_id; /* instance number of SI2OCP unit */ 75 int hw_dma_cfg; /* HW or SW DMA config flag */ 76 int hw_dma_start; /* HW or SW DMA start/stop flag */ 77 78 u32 *buffer_tag_list; /* list of the buffer tags available */ 79 u32 *csize_list; /* list of the valid CSIZE values */ 80}; 81 82struct scc_dma_state { 83 u32 scc_id:8; /* SCC id */ 84 u32 dma_id:8; /* DMA id, used for match with array idx*/ 85 u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */ 86 u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/ 87 u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/ 88 u32 dma_cmd:4; /* last executed command on this DMA */ 89}; 90 91union scc_cmd { 92 u32 reg; 93 struct { 94 u32 res1:19; /* reserved */ 95 u32 drs:1; /* DMA Register Set */ 96 u32 rid:2; /* Register Identifier */ 97 u32 id:6; /* DMA Identifier */ 98 u32 action:4; /* DMA Command encoding */ 99 } bits; 100}; 101 102union scc_dma_cfg { 103 u32 reg; 104 struct { 105 u32 res1:17; /* reserved */ 106 u32 agu_mode:1; /* AGU Mode */ 107 u32 res2:1; /* reserved */ 108 u32 fh_mode:1; /* Fifo Handler */ 109 u32 buffer_type:1; /* Defines type of mem buffers */ 110 u32 mci_cfg_id:1; /* MCI_CFG register selector */ 111 u32 packet_cfg_id:1; /* PACKET_CFG register selector */ 112 u32 buffer_id:8; /* DMA Buffer Identifier */ 113 } bits; 114}; 115 116union scc_debug { 117 u32 reg; 118 struct { 119 u32 res1:20; /* reserved */ 120 u32 arg:8; /* SCC Debug Command Argument (#) */ 121 u32 cmd:4; /* SCC Debug Command Register */ 122 } bits; 123}; 124 125union scc_softwareconfiguration { 126 u32 reg; 127 struct { 128 u32 res1:28; /* reserved */ 129 u32 clock_status:1; /* clock on/off */ 130 u32 packet_select:1; /* active SCC packet id */ 131 u32 enable_status:1; /* enabled [1/0] */ 132 u32 active_status:1; /* 1=active 0=reset */ 133 } bits; 134}; 135 136/* 137 * System on Chip Channel ID 138 */ 139enum scc_id { 140 SCC_NULL = -1, /* illegal SCC identifier */ 141 SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */ 142 SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */ 143 SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */ 144 SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */ 145 SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */ 146 SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */ 147 SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */ 148 SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */ 149 SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */ 150 SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */ 151 SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */ 152 SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */ 153 SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */ 154 SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */ 155 SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */ 156 SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */ 157 SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */ 158 SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */ 159 SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */ 160 SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */ 161 SCC_TSIO_WR, /* SCC_TSIO Write channel */ 162 SCC_TSIO_RD, /* SCC_TSIO Read channel */ 163 SCC_TSD_WR, /* SCC_TSD Write channel */ 164 SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */ 165 SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */ 166 SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */ 167 SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */ 168 SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */ 169 SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */ 170 SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */ 171 SCC_GA_WR, /* SCC_GA Write channel */ 172 SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */ 173 SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */ 174 SCC_AD_RD, /* SCC_AD Read channel */ 175 SCC_AD_WR, /* SCC_AD Write channel */ 176 SCC_ABP_RD, /* SCC_ABP Read channel */ 177 SCC_ABP_WR, /* SCC_ABP Write channel */ 178 SCC_EBI_RW, /* SCC_EBI Read/Write channel */ 179 SCC_USB_RW, /* SCC_USB Read/Write channel */ 180 SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */ 181 SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */ 182 SCC_MAX /* maximum limit on the SCC id */ 183}; 184 185int scc_set_usb_address_generation_mode(u32 agu_mode); 186int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs); 187int scc_setup_dma(enum scc_id id, u32 buffer_tag, 188 u32 type, u32 fh_mode, u32 drs, u32 dma_id); 189int scc_enable(enum scc_id id, u32 value); 190int scc_reset(enum scc_id id, u32 value); 191 192#endif /* _SCC_H */ 193