LXR uboot/board/ti/am57xx/mux

   1/*
   2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3 *
   4 * Author: Felipe Balbi <balbi@ti.com>
   5 *
   6 * Based on board/ti/dra7xx/evm.c
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10#ifndef _MUX_DATA_BEAGLE_X15_H_
  11#define _MUX_DATA_BEAGLE_X15_H_
  12
  13#include <asm/arch/mux_dra7xx.h>
  14
  15const struct pad_conf_entry core_padconf_array_essential_x15[] = {
  16        {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad0.vin3a_d0 */
  17        {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad1.vin3a_d1 */
  18        {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad2.vin3a_d2 */
  19        {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad3.vin3a_d3 */
  20        {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad4.vin3a_d4 */
  21        {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad5.vin3a_d5 */
  22        {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad6.vin3a_d6 */
  23        {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad7.vin3a_d7 */
  24        {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad8.vin3a_d8 */
  25        {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_ad9.vin3a_d9 */
  26        {GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad10.vin3a_d10 */
  27        {GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad11.vin3a_d11 */
  28        {GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad12.vin3a_d12 */
  29        {GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad13.vin3a_d13 */
  30        {GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad14.vin3a_d14 */
  31        {GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)},    /* gpmc_ad15.vin3a_d15 */
  32        {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a0.vin3a_d16 */
  33        {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a1.vin3a_d17 */
  34        {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a2.vin3a_d18 */
  35        {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a3.vin3a_d19 */
  36        {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a4.vin3a_d20 */
  37        {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a5.vin3a_d21 */
  38        {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a6.vin3a_d22 */
  39        {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a7.vin3a_d23 */
  40        {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a8.vin3a_hsync0 */
  41        {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_a9.vin3a_vsync0 */
  42        {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_a10.vin3a_de0 */
  43        {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_a11.vin3a_fld0 */
  44        {GPMC_A12, (M14 | PIN_INPUT_PULLUP)},   /* gpmc_a12.gpio2_2 */
  45        {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
  46        {GPMC_A14, (M14 | PIN_INPUT_PULLUP)},   /* gpmc_a14.gpio2_4 */
  47        {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
  48        {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
  49        {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
  50        {GPMC_A18, (M14 | PIN_INPUT_PULLUP)},   /* gpmc_a18.gpio2_8 */
  51        {GPMC_A19, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a19.mmc2_dat4 */
  52        {GPMC_A20, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a20.mmc2_dat5 */
  53        {GPMC_A21, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a21.mmc2_dat6 */
  54        {GPMC_A22, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a22.mmc2_dat7 */
  55        {GPMC_A23, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a23.mmc2_clk */
  56        {GPMC_A24, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a24.mmc2_dat0 */
  57        {GPMC_A25, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a25.mmc2_dat1 */
  58        {GPMC_A26, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a26.mmc2_dat2 */
  59        {GPMC_A27, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a27.mmc2_dat3 */
  60        {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_cs1.mmc2_cmd */
  61        {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
  62        {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)},   /* gpmc_cs2.gpio2_20 */
  63        {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_cs3.vin3a_clk0 */
  64        {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},  /* gpmc_clk.dma_evt1 */
  65        {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},      /* gpmc_advn_ale.gpio2_23 */
  66        {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)},       /* gpmc_oen_ren.gpio2_24 */
  67        {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)},   /* gpmc_wen.gpio2_25 */
  68        {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
  69        {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
  70        {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /* gpmc_wait0.gpio2_28 */
  71        {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)},   /* vin1b_clk1.gpio2_31 */
  72        {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
  73        {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
  74        {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
  75        {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
  76        {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
  77        {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
  78        {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
  79        {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d10.gpio3_14 */
  80        {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d11.gpio3_15 */
  81        {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d12.gpio3_16 */
  82        {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d14.gpio3_18 */
  83        {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d16.gpio3_20 */
  84        {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d19.gpio3_23 */
  85        {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d20.gpio3_24 */
  86        {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d22.gpio3_26 */
  87        {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)},       /* vin2a_clk0.gpio3_28 */
  88        {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)},        /* vin2a_de0.gpio3_29 */
  89        {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},       /* vin2a_fld0.gpio3_30 */
  90        {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)},       /* vin2a_hsync0.pr1_uart0_cts_n */
  91        {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)},      /* vin2a_vsync0.pr1_uart0_rts_n */
  92        {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)},   /* vin2a_d0.pr1_uart0_rxd */
  93        {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
  94        {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)},    /* vin2a_d2.uart10_rxd */
  95        {VIN2A_D3, (M8 | PIN_OUTPUT)},  /* vin2a_d3.uart10_txd */
  96        {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)},    /* vin2a_d4.uart10_ctsn */
  97        {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)},   /* vin2a_d5.uart10_rtsn */
  98        {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
  99        {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
 100        {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
 101        {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
 102        {VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)},       /* vin2a_d10.ehrpwm2B */
 103        {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)},        /* vin2a_d11.ehrpwm2_tripzone_input */
 104        {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d12.rgmii1_txc */
 105        {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d13.rgmii1_txctl */
 106        {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d14.rgmii1_txd3 */
 107        {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d15.rgmii1_txd2 */
 108        {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d16.rgmii1_txd1 */
 109        {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},   /* vin2a_d17.rgmii1_txd0 */
 110        {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d18.rgmii1_rxc */
 111        {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d19.rgmii1_rxctl */
 112        {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d20.rgmii1_rxd3 */
 113        {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d21.rgmii1_rxd2 */
 114        {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d22.rgmii1_rxd1 */
 115        {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},    /* vin2a_d23.rgmii1_rxd0 */
 116        {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
 117        {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* mdio_mclk.mdio_mclk */
 118        {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},       /* mdio_d.mdio_d */
 119        {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},    /* RMII_MHZ_50_CLK.gpio5_17 */
 120        {UART3_RXD, (M14 | PIN_INPUT_SLEW)},    /* uart3_rxd.gpio5_18 */
 121        {UART3_TXD, (M14 | PIN_INPUT_SLEW)},    /* uart3_txd.gpio5_19 */
 122        {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},  /* rgmii0_txc.rgmii0_txc */
 123        {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},        /* rgmii0_txctl.rgmii0_txctl */
 124        {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
 125        {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
 126        {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
 127        {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
 128        {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},   /* rgmii0_rxc.rgmii0_rxc */
 129        {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
 130        {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},  /* rgmii0_rxd3.rgmii0_rxd3 */
 131        {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},  /* rgmii0_rxd2.rgmii0_rxd2 */
 132        {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},  /* rgmii0_rxd1.rgmii0_rxd1 */
 133        {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},  /* rgmii0_rxd0.rgmii0_rxd0 */
 134        {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},        /* usb1_drvvbus.usb1_drvvbus */
 135        {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},       /* usb2_drvvbus.usb2_drvvbus */
 136        {GPIO6_14, (M10 | PIN_INPUT_PULLUP)},   /* gpio6_14.timer1 */
 137        {GPIO6_15, (M10 | PIN_INPUT_PULLUP)},   /* gpio6_15.timer2 */
 138        {GPIO6_16, (M10 | PIN_INPUT_PULLUP)},   /* gpio6_16.timer3 */
 139        {XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)},        /* xref_clk0.clkout2 */
 140        {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},        /* xref_clk1.gpio6_18 */
 141        {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},        /* xref_clk2.gpio6_19 */
 142        {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},        /* xref_clk3.clkout3 */
 143        {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)},       /* mcasp1_aclkx.i2c3_sda */
 144        {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /* mcasp1_fsx.i2c3_scl */
 145        {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)},       /* mcasp1_aclkr.i2c4_sda */
 146        {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
 147        {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr0.i2c5_sda */
 148        {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr1.i2c5_scl */
 149        {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr2.gpio5_4 */
 150        {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr3.gpio5_5 */
 151        {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr4.gpio5_6 */
 152        {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr5.gpio5_7 */
 153        {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr6.gpio5_8 */
 154        {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr7.gpio5_9 */
 155        {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */
 156        {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */
 157        {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)},        /* mcasp1_axr10.gpio5_12 */
 158        {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
 159        {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
 160        {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
 161        {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
 162        {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
 163        {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},      /* mcasp3_aclkx.mcasp3_aclkx */
 164        {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},    /* mcasp3_fsx.mcasp3_fsx */
 165        {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},   /* mcasp3_axr0.mcasp3_axr0 */
 166        {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)},   /* mcasp3_axr1.mcasp3_axr1 */
 167        {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)},        /* mcasp4_aclkx.uart8_rxd */
 168        {MCASP4_FSX, (M3 | PIN_OUTPUT)},        /* mcasp4_fsx.uart8_txd */
 169        {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */
 170        {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)},        /* mcasp4_axr1.uart8_rtsn */
 171        {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)},        /* mcasp5_aclkx.uart9_rxd */
 172        {MCASP5_FSX, (M3 | PIN_OUTPUT)},        /* mcasp5_fsx.uart9_txd */
 173        {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */
 174        {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)},        /* mcasp5_axr1.uart9_rtsn */
 175        {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_clk.mmc1_clk */
 176        {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_cmd.mmc1_cmd */
 177        {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat0.mmc1_dat0 */
 178        {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat1.mmc1_dat1 */
 179        {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat2.mmc1_dat2 */
 180        {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat3.mmc1_dat3 */
 181        {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},    /* mmc1_sdcd.gpio6_27 */
 182        {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)},        /* gpio6_10.ehrpwm2A */
 183        {GPIO6_11, (M0 | PIN_INPUT_PULLUP)},    /* gpio6_11.gpio6_11 */
 184        {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /* mmc3_clk.mmc3_clk */
 185        {MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /* mmc3_cmd.mmc3_cmd */
 186        {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat0.mmc3_dat0 */
 187        {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat1.mmc3_dat1 */
 188        {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat2.mmc3_dat2 */
 189        {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat3.mmc3_dat3 */
 190        {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat4.mmc3_dat4 */
 191        {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat5.mmc3_dat5 */
 192        {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat6.mmc3_dat6 */
 193        {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* mmc3_dat7.mmc3_dat7 */
 194        {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},        /* spi1_sclk.gpio7_7 */
 195        {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},  /* spi1_d1.gpio7_8 */
 196        {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},  /* spi1_d0.gpio7_9 */
 197        {SPI1_CS0, (M14 | PIN_INPUT)},  /* spi1_cs0.gpio7_10 */
 198        {SPI1_CS1, (M14 | PIN_INPUT)},  /* spi1_cs1.gpio7_11 */
 199        {SPI1_CS2, (M14 | PIN_INPUT_SLEW)},     /* spi1_cs2.gpio7_12 */
 200        {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},      /* spi1_cs3.hdmi1_cec */
 201        {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)},        /* spi2_sclk.gpio7_14 */
 202        {SPI2_D1, (M14 | PIN_INPUT_SLEW)},      /* spi2_d1.gpio7_15 */
 203        {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},      /* spi2_d0.gpio7_16 */
 204        {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},     /* spi2_cs0.gpio7_17 */
 205        {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* dcan1_tx.dcan1_tx */
 206        {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)},     /* dcan1_rx.dcan1_rx */
 207        {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},     /* uart1_rxd.uart1_rxd */
 208        {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* uart1_txd.uart1_txd */
 209        {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)},       /* uart1_ctsn.gpio7_24 */
 210        {UART1_RTSN, (M14 | PIN_INPUT)},        /* uart1_rtsn.gpio7_25 */
 211        {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)},        /* uart2_rxd.gpio7_26 */
 212        {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)},        /* uart2_txd.gpio7_27 */
 213        {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)},  /* uart2_ctsn.uart3_rxd */
 214        {UART2_RTSN, (M1 | PIN_OUTPUT)},        /* uart2_rtsn.uart3_txd */
 215        {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)},    /* i2c1_sda.i2c1_sda */
 216        {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)},    /* i2c1_scl.i2c1_scl */
 217        {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},    /* i2c2_sda.hdmi1_ddc_scl */
 218        {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},    /* i2c2_scl.hdmi1_ddc_sda */
 219        {WAKEUP0, (M0 | PIN_INPUT)},    /* Wakeup0.Wakeup0 */
 220        {WAKEUP1, (M0 | PIN_INPUT)},    /* Wakeup1.Wakeup1 */
 221        {WAKEUP2, (M0 | PIN_INPUT)},    /* Wakeup2.Wakeup2 */
 222        {WAKEUP3, (M0 | PIN_INPUT)},    /* Wakeup3.Wakeup3 */
 223        {ON_OFF, (M0 | PIN_OUTPUT)},    /* on_off.on_off */
 224        {RTC_PORZ, (M0 | PIN_INPUT)},   /* rtc_porz.rtc_porz */
 225        {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
 226        {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /* tdi.tdi */
 227        {TDO, (M0 | PIN_OUTPUT)},       /* tdo.tdo */
 228        {TCLK, (M0 | PIN_INPUT_PULLDOWN)},      /* tclk.tclk */
 229        {TRSTN, (M0 | PIN_INPUT)},      /* trstn.trstn */
 230        {RTCK, (M0 | PIN_OUTPUT)},      /* rtck.rtck */
 231        {EMU0, (M0 | PIN_INPUT)},       /* emu0.emu0 */
 232        {EMU1, (M0 | PIN_INPUT)},       /* emu1.emu1 */
 233        {NMIN_DSP, (M0 | PIN_INPUT)},   /* nmin_dsp.nmin_dsp */
 234        {RSTOUTN, (M0 | PIN_OUTPUT)},   /* rstoutn.rstoutn */
 235};
 236
 237const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
 238        {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},   /* mmc1_sdwp.gpio6_28 */
 239        {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_clk.vout1_clk */
 240        {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_de.vout1_de */
 241        {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
 242        {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
 243        {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d0.vout1_d0 */
 244        {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d1.vout1_d1 */
 245        {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d2.vout1_d2 */
 246        {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d3.vout1_d3 */
 247        {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d4.vout1_d4 */
 248        {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d5.vout1_d5 */
 249        {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d6.vout1_d6 */
 250        {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d7.vout1_d7 */
 251        {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d8.vout1_d8 */
 252        {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d9.vout1_d9 */
 253        {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d10.vout1_d10 */
 254        {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d11.vout1_d11 */
 255        {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d12.vout1_d12 */
 256        {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d13.vout1_d13 */
 257        {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d14.vout1_d14 */
 258        {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d15.vout1_d15 */
 259        {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d16.vout1_d16 */
 260        {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d17.vout1_d17 */
 261        {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d18.vout1_d18 */
 262        {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d19.vout1_d19 */
 263        {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d20.vout1_d20 */
 264        {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d21.vout1_d21 */
 265        {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d22.vout1_d22 */
 266        {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d23.vout1_d23 */
 267};
 268
 269const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
 270        {VIN1A_CLK0, (M14 | PIN_INPUT)},        /* vin1a_clk0.gpio2_30 */
 271        {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_clk.vout1_clk */
 272        {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_de.vout1_de */
 273        {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},   /* vout1_hsync.vout1_hsync */
 274        {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},   /* vout1_vsync.vout1_vsync */
 275        {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d0.vout1_d0 */
 276        {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d1.vout1_d1 */
 277        {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d2.vout1_d2 */
 278        {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d3.vout1_d3 */
 279        {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d4.vout1_d4 */
 280        {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d5.vout1_d5 */
 281        {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d6.vout1_d6 */
 282        {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d7.vout1_d7 */
 283        {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d8.vout1_d8 */
 284        {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d9.vout1_d9 */
 285        {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d10.vout1_d10 */
 286        {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d11.vout1_d11 */
 287        {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d12.vout1_d12 */
 288        {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d13.vout1_d13 */
 289        {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d14.vout1_d14 */
 290        {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d15.vout1_d15 */
 291        {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d16.vout1_d16 */
 292        {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d17.vout1_d17 */
 293        {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d18.vout1_d18 */
 294        {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d19.vout1_d19 */
 295        {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d20.vout1_d20 */
 296        {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d21.vout1_d21 */
 297        {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d22.vout1_d22 */
 298        {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d23.vout1_d23 */
 299};
 300
 301const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
 302        {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a0.vin4b_d0 */
 303        {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a1.vin4b_d1 */
 304        {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a2.vin4b_d2 */
 305        {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a3.vin4b_d3 */
 306        {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a4.vin4b_d4 */
 307        {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a5.vin4b_d5 */
 308        {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a6.vin4b_d6 */
 309        {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a7.vin4b_d7 */
 310        {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a8.vin4b_hsync1 */
 311        {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a9.vin4b_vsync1 */
 312        {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a10.vin4b_clk1 */
 313        {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a11.vin4b_de1 */
 314        {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a12.vin4b_fld1 */
 315        {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a13.qspi1_rtclk */
 316        {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a14.qspi1_d3 */
 317        {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a15.qspi1_d2 */
 318        {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a16.qspi1_d0 */
 319        {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a17.qspi1_d1 */
 320        {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},    /* gpmc_a18.qspi1_sclk */
 321        {GPMC_A19, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a19.mmc2_dat4 */
 322        {GPMC_A20, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a20.mmc2_dat5 */
 323        {GPMC_A21, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a21.mmc2_dat6 */
 324        {GPMC_A22, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a22.mmc2_dat7 */
 325        {GPMC_A23, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a23.mmc2_clk */
 326        {GPMC_A24, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a24.mmc2_dat0 */
 327        {GPMC_A25, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a25.mmc2_dat1 */
 328        {GPMC_A26, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a26.mmc2_dat2 */
 329        {GPMC_A27, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a27.mmc2_dat3 */
 330        {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_cs1.mmc2_cmd */
 331        {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},    /* gpmc_cs2.qspi1_cs0 */
 332        {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
 333        {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
 334        {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
 335        {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
 336        {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},        /* vin1a_d10.gpio3_14 */
 337        {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
 338        {VIN1A_D13, (M14 | PIN_OUTPUT)},        /* vin1a_d13.gpio3_17 */
 339        {VIN1A_D14, (M14 | PIN_OUTPUT)},        /* vin1a_d14.gpio3_18 */
 340        {VIN1A_D15, (M14 | PIN_OUTPUT)},        /* vin1a_d15.gpio3_19 */
 341        {VIN1A_D17, (M14 | PIN_OUTPUT)},        /* vin1a_d17.gpio3_21 */
 342        {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)},       /* vin1a_d18.gpio3_22 */
 343        {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
 344        {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
 345        {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
 346        {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},  /* vin2a_de0.gpio3_29 */
 347        {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
 348        {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},       /* vin2a_hsync0.gpio3_31 */
 349        {VIN2A_VSYNC0, (M14 | PIN_INPUT)},      /* vin2a_vsync0.gpio4_0 */
 350        {VIN2A_D0, (M11 | PIN_INPUT)},  /* vin2a_d0.pr1_uart0_rxd */
 351        {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
 352        {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
 353        {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
 354        {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
 355        {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d5.pr1_pru1_gpo2 */
 356        {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},       /* vin2a_d10.pr1_mdio_mdclk */
 357        {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
 358        {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d12.rgmii1_txc */
 359        {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d13.rgmii1_txctl */
 360        {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d14.rgmii1_txd3 */
 361        {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d15.rgmii1_txd2 */
 362        {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d16.rgmii1_txd1 */
 363        {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d17.rgmii1_txd0 */
 364        {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* vin2a_d18.rgmii1_rxc */
 365        {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* vin2a_d19.rgmii1_rxctl */
 366        {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d20.rgmii1_rxd3 */
 367        {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d21.rgmii1_rxd2 */
 368        {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d22.rgmii1_rxd1 */
 369        {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d23.rgmii1_rxd0 */
 370        {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_clk.vout1_clk */
 371        {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_de.vout1_de */
 372        {VOUT1_FLD, (M14 | PIN_OUTPUT)},        /* vout1_fld.gpio4_21 */
 373        {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},   /* vout1_hsync.vout1_hsync */
 374        {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},   /* vout1_vsync.vout1_vsync */
 375        {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d0.vout1_d0 */
 376        {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d1.vout1_d1 */
 377        {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d2.vout1_d2 */
 378        {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d3.vout1_d3 */
 379        {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d4.vout1_d4 */
 380        {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d5.vout1_d5 */
 381        {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d6.vout1_d6 */
 382        {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d7.vout1_d7 */
 383        {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d8.vout1_d8 */
 384        {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},      /* vout1_d9.vout1_d9 */
 385        {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d10.vout1_d10 */
 386        {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d11.vout1_d11 */
 387        {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d12.vout1_d12 */
 388        {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d13.vout1_d13 */
 389        {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d14.vout1_d14 */
 390        {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d15.vout1_d15 */
 391        {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d16.vout1_d16 */
 392        {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d17.vout1_d17 */
 393        {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d18.vout1_d18 */
 394        {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d19.vout1_d19 */
 395        {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d20.vout1_d20 */
 396        {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d21.vout1_d21 */
 397        {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d22.vout1_d22 */
 398        {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},     /* vout1_d23.vout1_d23 */
 399        {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)},     /* mdio_mclk.mdio_mclk */
 400        {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},       /* mdio_d.mdio_d */
 401        {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
 402        {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},       /* rgmii0_txctl.rgmii0_txctl */
 403        {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd3.rgmii0_txd3 */
 404        {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd2.rgmii0_txd2 */
 405        {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd1.rgmii0_txd1 */
 406        {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd0.rgmii0_txd0 */
 407        {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* rgmii0_rxc.rgmii0_rxc */
 408        {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_rxctl.rgmii0_rxctl */
 409        {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd3.rgmii0_rxd3 */
 410        {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd2.rgmii0_rxd2 */
 411        {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd1.rgmii0_rxd1 */
 412        {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd0.rgmii0_rxd0 */
 413        {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},        /* usb1_drvvbus.usb1_drvvbus */
 414        {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},        /* usb2_drvvbus.usb2_drvvbus */
 415        {GPIO6_14, (M0 | PIN_OUTPUT)},  /* gpio6_14.gpio6_14 */
 416        {GPIO6_15, (M0 | PIN_OUTPUT)},  /* gpio6_15.gpio6_15 */
 417        {GPIO6_16, (M0 | PIN_INPUT_PULLUP)},    /* gpio6_16.gpio6_16 */
 418        {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},        /* xref_clk0.pr2_mii1_col */
 419        {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},        /* xref_clk1.pr2_mii1_crs */
 420        {XREF_CLK2, (M14 | PIN_OUTPUT)},        /* xref_clk2.gpio6_19 */
 421        {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},        /* xref_clk3.clkout3 */
 422        {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},    /* mcasp1_aclkx.pr2_mdio_mdclk */
 423        {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},  /* mcasp1_fsx.pr2_mdio_data */
 424        {MCASP1_ACLKR, (M14 | PIN_INPUT)},      /* mcasp1_aclkr.gpio5_0 */
 425        {MCASP1_FSR, (M14 | PIN_INPUT)},        /* mcasp1_fsr.gpio5_1 */
 426        {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr0.pr2_mii0_rxer */
 427        {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr1.pr2_mii_mt0_clk */
 428        {MCASP1_AXR2, (M14 | PIN_INPUT)},       /* mcasp1_axr2.gpio5_4 */
 429        {MCASP1_AXR3, (M14 | PIN_INPUT)},       /* mcasp1_axr3.gpio5_5 */
 430        {MCASP1_AXR4, (M14 | PIN_OUTPUT)},      /* mcasp1_axr4.gpio5_6 */
 431        {MCASP1_AXR5, (M14 | PIN_OUTPUT)},      /* mcasp1_axr5.gpio5_7 */
 432        {MCASP1_AXR6, (M14 | PIN_OUTPUT)},      /* mcasp1_axr6.gpio5_8 */
 433        {MCASP1_AXR7, (M14 | PIN_OUTPUT)},      /* mcasp1_axr7.gpio5_9 */
 434        {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
 435        {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
 436        {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr10.pr2_mii0_txd2 */
 437        {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr11.pr2_mii0_txd1 */
 438        {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr12.pr2_mii0_txd0 */
 439        {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
 440        {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
 441        {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
 442        {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},     /* mcasp2_aclkx.pr2_mii0_rxd2 */
 443        {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp2_fsx.pr2_mii0_rxd1 */
 444        {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},  /* mcasp2_axr2.pr2_mii0_rxd0 */
 445        {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},  /* mcasp2_axr3.pr2_mii0_rxlink */
 446        {MCASP2_AXR4, (M14 | PIN_OUTPUT)},      /* mcasp2_axr4.gpio1_4 */
 447        {MCASP2_AXR5, (M14 | PIN_OUTPUT)},      /* mcasp2_axr5.gpio6_7 */
 448        {MCASP2_AXR6, (M14 | PIN_OUTPUT)},      /* mcasp2_axr6.gpio2_29 */
 449        {MCASP2_AXR7, (M14 | PIN_OUTPUT)},      /* mcasp2_axr7.gpio1_5 */
 450        {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},     /* mcasp3_aclkx.pr2_mii0_crs */
 451        {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp3_fsx.pr2_mii0_col */
 452        {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp3_axr0.pr2_mii1_rxer */
 453        {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp3_axr1.pr2_mii1_rxlink */
 454        {MCASP4_ACLKX, (M2 | PIN_INPUT)},       /* mcasp4_aclkx.spi3_sclk */
 455        {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
 456        {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
 457        {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)},       /* mcasp5_aclkx.pr2_pru1_gpo1 */
 458        {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},  /* mcasp5_fsx.pr2_pru1_gpi2 */
 459        {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_clk.mmc1_clk */
 460        {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_cmd.mmc1_cmd */
 461        {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat0.mmc1_dat0 */
 462        {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat1.mmc1_dat1 */
 463        {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat2.mmc1_dat2 */
 464        {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat3.mmc1_dat3 */
 465        {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},   /* mmc1_sdcd.gpio6_27 */
 466        {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},   /* mmc1_sdwp.gpio6_28 */
 467        {GPIO6_10, (M11 | PIN_INPUT_PULLUP)},   /* gpio6_10.pr2_mii_mt1_clk */
 468        {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},  /* gpio6_11.pr2_mii1_txen */
 469        {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},  /* mmc3_clk.pr2_mii1_txd3 */
 470        {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},  /* mmc3_cmd.pr2_mii1_txd2 */
 471        {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
 472        {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
 473        {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},  /* mmc3_dat2.pr2_mii_mr1_clk */
 474        {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat3.pr2_mii1_rxdv */
 475        {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat4.pr2_mii1_rxd3 */
 476        {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat5.pr2_mii1_rxd2 */
 477        {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat6.pr2_mii1_rxd1 */
 478        {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat7.pr2_mii1_rxd0 */
 479        {SPI1_SCLK, (M14 | PIN_OUTPUT)},        /* spi1_sclk.gpio7_7 */
 480        {SPI1_D1, (M14 | PIN_OUTPUT)},  /* spi1_d1.gpio7_8 */
 481        {SPI1_D0, (M14 | PIN_OUTPUT)},  /* spi1_d0.gpio7_9 */
 482        {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
 483        {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
 484        {SPI1_CS2, (M14 | PIN_INPUT_SLEW)},     /* spi1_cs2.gpio7_12 */
 485        {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},      /* spi1_cs3.hdmi1_cec */
 486        {SPI2_SCLK, (M0 | PIN_INPUT)},  /* spi2_sclk.spi2_sclk */
 487        {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},      /* spi2_d1.spi2_d1 */
 488        {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},      /* spi2_d0.spi2_d0 */
 489        {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},     /* spi2_cs0.spi2_cs0 */
 490        {DCAN1_TX, (M15 | PULL_UP)},    /* dcan1_tx.safe for dcan1_tx */
 491        {DCAN1_RX, (M15 | PULL_UP)},    /* dcan1_rx.safe for dcan1_rx */
 492        {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},  /* uart1_rxd.gpio7_22 */
 493        {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},  /* uart1_txd.gpio7_23 */
 494        {UART2_RXD, (M4 | PIN_INPUT)},  /* uart2_rxd.uart2_rxd */
 495        {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
 496        {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
 497        {UART2_RTSN, (M1 | PIN_OUTPUT)},        /* uart2_rtsn.uart3_txd */
 498        {I2C1_SDA, (M0 | PIN_INPUT)},   /* i2c1_sda.i2c1_sda */
 499        {I2C1_SCL, (M0 | PIN_INPUT)},   /* i2c1_scl.i2c1_scl */
 500        {I2C2_SDA, (M1 | PIN_INPUT)},   /* i2c2_sda.hdmi1_ddc_scl */
 501        {I2C2_SCL, (M1 | PIN_INPUT)},   /* i2c2_scl.hdmi1_ddc_sda */
 502        {WAKEUP0, (M0 | PIN_INPUT)},    /* Wakeup0.Wakeup0 */
 503        {WAKEUP1, (M0 | PIN_INPUT)},    /* Wakeup1.Wakeup1 */
 504        {WAKEUP2, (M0 | PIN_INPUT)},    /* Wakeup2.Wakeup2 */
 505        {WAKEUP3, (M0 | PIN_INPUT)},    /* Wakeup3.Wakeup3 */
 506        {ON_OFF, (M0 | PIN_OUTPUT)},    /* on_off.on_off */
 507        {RTC_PORZ, (M0 | PIN_INPUT)},   /* rtc_porz.rtc_porz */
 508        {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
 509        {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /* tdi.tdi */
 510        {TDO, (M0 | PIN_OUTPUT_PULLUP)},        /* tdo.tdo */
 511        {TCLK, (M0 | PIN_INPUT_PULLUP)},        /* tclk.tclk */
 512        {TRSTN, (M0 | PIN_INPUT_PULLDOWN)},     /* trstn.trstn */
 513        {RTCK, (M0 | PIN_OUTPUT_PULLUP)},       /* rtck.rtck */
 514        {EMU0, (M0 | PIN_INPUT_PULLUP)},        /* emu0.emu0 */
 515        {EMU1, (M0 | PIN_INPUT_PULLUP)},        /* emu1.emu1 */
 516        {RESETN, (M0 | PIN_INPUT)},     /* resetn.resetn */
 517        {NMIN_DSP, (M0 | PIN_INPUT)},   /* nmin_dsp.nmin_dsp */
 518        {RSTOUTN, (M0 | PIN_OUTPUT)},   /* rstoutn.rstoutn */
 519};
 520
 521const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
 522        {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a0.vin1b_d0 */
 523        {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a1.vin1b_d1 */
 524        {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a2.vin1b_d2 */
 525        {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a3.vin1b_d3 */
 526        {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a4.vin1b_d4 */
 527        {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a5.vin1b_d5 */
 528        {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a6.vin1b_d6 */
 529        {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a7.vin1b_d7 */
 530        {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a8.vin1b_hsync1 */
 531        {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},      /* gpmc_a9.vin1b_vsync1 */
 532        {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a10.vin1b_clk1 */
 533        {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a11.vin1b_de1 */
 534        {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a12.vin1b_fld1 */
 535        {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a13.qspi1_rtclk */
 536        {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a14.qspi1_d3 */
 537        {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a15.qspi1_d2 */
 538        {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a16.qspi1_d0 */
 539        {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},     /* gpmc_a17.qspi1_d1 */
 540        {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},    /* gpmc_a18.qspi1_sclk */
 541        {GPMC_A19, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a19.mmc2_dat4 */
 542        {GPMC_A20, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a20.mmc2_dat5 */
 543        {GPMC_A21, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a21.mmc2_dat6 */
 544        {GPMC_A22, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a22.mmc2_dat7 */
 545        {GPMC_A23, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a23.mmc2_clk */
 546        {GPMC_A24, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a24.mmc2_dat0 */
 547        {GPMC_A25, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a25.mmc2_dat1 */
 548        {GPMC_A26, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a26.mmc2_dat2 */
 549        {GPMC_A27, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_a27.mmc2_dat3 */
 550        {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},    /* gpmc_cs1.mmc2_cmd */
 551        {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */
 552        {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},    /* gpmc_cs2.qspi1_cs0 */
 553        {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */
 554        {GPMC_CLK, (M14 | PIN_INPUT)},  /* gpmc_clk.gpio2_22 */
 555        {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)},    /* gpmc_advn_ale.gpio2_23 */
 556        {GPMC_OEN_REN, (M14 | PIN_OUTPUT)},     /* gpmc_oen_ren.gpio2_24 */
 557        {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */
 558        {GPMC_BEN0, (M14 | PIN_OUTPUT)},        /* gpmc_ben0.gpio2_26 */
 559        {GPMC_BEN1, (M14 | PIN_OUTPUT)},        /* gpmc_ben1.gpio2_27 */
 560        {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
 561        {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
 562        {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},  /* vin2a_de0.gpio3_29 */
 563        {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
 564        {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},       /* vin2a_hsync0.gpio3_31 */
 565        {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)},     /* vin2a_vsync0.gpio4_0 */
 566        {VIN2A_D0, (M11 | PIN_INPUT)},  /* vin2a_d0.pr1_uart0_rxd */
 567        {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
 568        {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
 569        {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},       /* vin2a_d10.pr1_mdio_mdclk */
 570        {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
 571        {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d12.rgmii1_txc */
 572        {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d13.rgmii1_txctl */
 573        {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d14.rgmii1_txd3 */
 574        {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d15.rgmii1_txd2 */
 575        {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d16.rgmii1_txd1 */
 576        {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d17.rgmii1_txd0 */
 577        {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* vin2a_d18.rgmii1_rxc */
 578        {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* vin2a_d19.rgmii1_rxctl */
 579        {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d20.rgmii1_rxd3 */
 580        {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d21.rgmii1_rxd2 */
 581        {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d22.rgmii1_rxd1 */
 582        {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* vin2a_d23.rgmii1_rxd0 */
 583        {VOUT1_FLD, (M14 | PIN_OUTPUT)},        /* vout1_fld.gpio4_21 */
 584        {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},  /* mdio_mclk.mdio_mclk */
 585        {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},       /* mdio_d.mdio_d */
 586        {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},   /* uart3_rxd.gpio5_18 */
 587        {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */
 588        {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
 589        {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},       /* rgmii0_txctl.rgmii0_txctl */
 590        {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd3.rgmii0_txd3 */
 591        {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd2.rgmii0_txd2 */
 592        {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd1.rgmii0_txd1 */
 593        {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txd0.rgmii0_txd0 */
 594        {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* rgmii0_rxc.rgmii0_rxc */
 595        {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_rxctl.rgmii0_rxctl */
 596        {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd3.rgmii0_rxd3 */
 597        {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd2.rgmii0_rxd2 */
 598        {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd1.rgmii0_rxd1 */
 599        {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd0.rgmii0_rxd0 */
 600        {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},        /* usb1_drvvbus.usb1_drvvbus */
 601        {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},        /* usb2_drvvbus.usb2_drvvbus */
 602        {GPIO6_14, (M0 | PIN_OUTPUT)},  /* gpio6_14.gpio6_14 */
 603        {GPIO6_15, (M0 | PIN_OUTPUT)},  /* gpio6_15.gpio6_15 */
 604        {GPIO6_16, (M0 | PIN_INPUT_PULLUP)},    /* gpio6_16.gpio6_16 */
 605        {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},        /* xref_clk0.pr2_mii1_col */
 606        {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},        /* xref_clk1.pr2_mii1_crs */
 607        {XREF_CLK2, (M14 | PIN_OUTPUT)},        /* xref_clk2.gpio6_19 */
 608        {XREF_CLK3, (M7 | PIN_INPUT)},  /* xref_clk3.hdq0 */
 609        {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},    /* mcasp1_aclkx.pr2_mdio_mdclk */
 610        {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},  /* mcasp1_fsx.pr2_mdio_data */
 611        {MCASP1_ACLKR, (M14 | PIN_INPUT)},      /* mcasp1_aclkr.gpio5_0 */
 612        {MCASP1_FSR, (M14 | PIN_INPUT)},        /* mcasp1_fsr.gpio5_1 */
 613        {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr0.pr2_mii0_rxer */
 614        {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp1_axr1.pr2_mii_mt0_clk */
 615        {MCASP1_AXR2, (M14 | PIN_INPUT)},       /* mcasp1_axr2.gpio5_4 */
 616        {MCASP1_AXR3, (M14 | PIN_INPUT)},       /* mcasp1_axr3.gpio5_5 */
 617        {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},      /* mcasp1_axr4.gpio5_6 */
 618        {MCASP1_AXR5, (M14 | PIN_INPUT)},       /* mcasp1_axr5.gpio5_7 */
 619        {MCASP1_AXR6, (M14 | PIN_OUTPUT)},      /* mcasp1_axr6.gpio5_8 */
 620        {MCASP1_AXR7, (M14 | PIN_OUTPUT)},      /* mcasp1_axr7.gpio5_9 */
 621        {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
 622        {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
 623        {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr10.pr2_mii0_txd2 */
 624        {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr11.pr2_mii0_txd1 */
 625        {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},        /* mcasp1_axr12.pr2_mii0_txd0 */
 626        {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
 627        {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
 628        {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
 629        {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},     /* mcasp2_aclkx.pr2_mii0_rxd2 */
 630        {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp2_fsx.pr2_mii0_rxd1 */
 631        {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},  /* mcasp2_axr2.pr2_mii0_rxd0 */
 632        {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},  /* mcasp2_axr3.pr2_mii0_rxlink */
 633        {MCASP2_AXR4, (M14 | PIN_OUTPUT)},      /* mcasp2_axr4.gpio1_4 */
 634        {MCASP2_AXR5, (M14 | PIN_OUTPUT)},      /* mcasp2_axr5.gpio6_7 */
 635        {MCASP2_AXR6, (M14 | PIN_OUTPUT)},      /* mcasp2_axr6.gpio2_29 */
 636        {MCASP2_AXR7, (M14 | PIN_OUTPUT)},      /* mcasp2_axr7.gpio1_5 */
 637        {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},     /* mcasp3_aclkx.pr2_mii0_crs */
 638        {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},   /* mcasp3_fsx.pr2_mii0_col */
 639        {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp3_axr0.pr2_mii1_rxer */
 640        {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* mcasp3_axr1.pr2_mii1_rxlink */
 641        {MCASP4_ACLKX, (M2 | PIN_OUTPUT)},      /* mcasp4_aclkx.spi3_sclk */
 642        {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
 643        {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)},        /* mcasp4_axr1.spi3_cs0 */
 644        {MCASP5_AXR0, (M4 | PIN_INPUT)},        /* mcasp5_axr0.uart3_rxd */
 645        {MCASP5_AXR1, (M4 | PIN_OUTPUT)},       /* mcasp5_axr1.uart3_txd */
 646        {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_clk.mmc1_clk */
 647        {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_cmd.mmc1_cmd */
 648        {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat0.mmc1_dat0 */
 649        {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat1.mmc1_dat1 */
 650        {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat2.mmc1_dat2 */
 651        {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat3.mmc1_dat3 */
 652        {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},   /* mmc1_sdcd.gpio6_27 */
 653        {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},   /* mmc1_sdwp.gpio6_28 */
 654        {GPIO6_10, (M11 | PIN_INPUT_PULLUP)},   /* gpio6_10.pr2_mii_mt1_clk */
 655        {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},  /* gpio6_11.pr2_mii1_txen */
 656        {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},  /* mmc3_clk.pr2_mii1_txd3 */
 657        {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},  /* mmc3_cmd.pr2_mii1_txd2 */
 658        {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
 659        {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
 660        {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},  /* mmc3_dat2.pr2_mii_mr1_clk */
 661        {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat3.pr2_mii1_rxdv */
 662        {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat4.pr2_mii1_rxd3 */
 663        {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat5.pr2_mii1_rxd2 */
 664        {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat6.pr2_mii1_rxd1 */
 665        {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},        /* mmc3_dat7.pr2_mii1_rxd0 */
 666        {SPI1_SCLK, (M14 | PIN_OUTPUT)},        /* spi1_sclk.gpio7_7 */
 667        {SPI1_D1, (M14 | PIN_OUTPUT)},  /* spi1_d1.gpio7_8 */
 668        {SPI1_D0, (M14 | PIN_OUTPUT)},  /* spi1_d0.gpio7_9 */
 669        {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
 670        {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
 671        {SPI1_CS2, (M14 | PIN_INPUT_SLEW)},     /* spi1_cs2.gpio7_12 */
 672        {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},     /* spi1_cs3.hdmi1_cec */
 673        {SPI2_SCLK, (M0 | PIN_INPUT)},  /* spi2_sclk.spi2_sclk */
 674        {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},      /* spi2_d1.spi2_d1 */
 675        {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},      /* spi2_d0.spi2_d0 */
 676        {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},     /* spi2_cs0.spi2_cs0 */
 677        {DCAN1_TX, (M15 | PULL_UP)},    /* dcan1_tx.safe for dcan1_tx */
 678        {DCAN1_RX, (M15 | PULL_UP)},    /* dcan1_rx.safe for dcan1_rx */
 679        {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)},   /* uart1_rxd.gpio7_22 */
 680        {UART1_CTSN, (M14 | PIN_OUTPUT)},       /* uart1_ctsn.gpio7_24 */
 681        {UART1_RTSN, (M14 | PIN_OUTPUT)},       /* uart1_rtsn.gpio7_25 */
 682        {I2C1_SDA, (M0 | PIN_INPUT)},   /* i2c1_sda.i2c1_sda */
 683        {I2C1_SCL, (M0 | PIN_INPUT)},   /* i2c1_scl.i2c1_scl */
 684        {I2C2_SDA, (M1 | PIN_INPUT)},   /* i2c2_sda.hdmi1_ddc_scl */
 685        {I2C2_SCL, (M1 | PIN_INPUT)},   /* i2c2_scl.hdmi1_ddc_sda */
 686        {WAKEUP0, (M0 | PIN_INPUT)},    /* Wakeup0.Wakeup0 */
 687        {WAKEUP3, (M0 | PIN_INPUT)},    /* Wakeup3.Wakeup3 */
 688        {ON_OFF, (M0 | PIN_OUTPUT)},    /* on_off.on_off */
 689        {RTC_PORZ, (M0 | PIN_INPUT)},   /* rtc_porz.rtc_porz */
 690        {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
 691        {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /* tdi.tdi */
 692        {TDO, (M0 | PIN_OUTPUT_PULLUP)},        /* tdo.tdo */
 693        {TCLK, (M0 | PIN_INPUT_PULLUP)},        /* tclk.tclk */
 694        {TRSTN, (M0 | PIN_INPUT)},      /* trstn.trstn */
 695        {RTCK, (M0 | PIN_OUTPUT_PULLUP)},       /* rtck.rtck */
 696        {EMU0, (M0 | PIN_INPUT)},       /* emu0.emu0 */
 697        {EMU1, (M0 | PIN_INPUT)},       /* emu1.emu1 */
 698        {RESETN, (M0 | PIN_INPUT)},     /* resetn.resetn */
 699        {RSTOUTN, (M0 | PIN_OUTPUT)},   /* rstoutn.rstoutn */
 700};
 701
 702const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
 703        /* PR1 MII0 */
 704        {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)},   /* vout1_d8.pr1_mii_mt0_clk */
 705        {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)},  /* vout1_d9.pr1_mii0_txd3 */
 706        {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */
 707        {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */
 708        {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */
 709        {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */
 710        {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)},  /* vout1_d14.pr1_mii_mr0_clk */
 711        {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d15.pr1_mii0_rxdv */
 712        {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d16.pr1_mii0_rxd3 */
 713        {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d17.pr1_mii0_rxd2 */
 714        {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d18.pr1_mii0_rxd1 */
 715        {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d19.pr1_mii0_rxd0 */
 716        {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)},  /* vout1_d20.pr1_mii0_rxer */
 717        {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d21.pr1_mii0_rxlink */
 718        {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d22.pr1_mii0_col */
 719        {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)},        /* vout1_d23.pr1_mii0_crs */
 720
 721        /* PR1 MII1 */
 722        {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */
 723        {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)},  /* vin2a_d4.pr1_mii1_txd1 */
 724        {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)},  /* vin2a_d5.pr1_mii1_txd0 */
 725        {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)},   /* vin2a_d6.pr1_mii_mt1_clk */
 726        {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)},  /* vin2a_d7.pr1_mii1_txen */
 727        {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)},  /* vin2a_d8.pr1_mii1_txd3 */
 728        {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)},  /* vin2a_d9.pr1_mii1_txd2 */
 729        {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)},        /* vout1_vsync.pr1_mii1_rxer */
 730        {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)},   /* vout1_d0.pr1_mii1_rxlink */
 731        {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */
 732        {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)},   /* vout1_d2.pr1_mii_mr1_clk */
 733        {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */
 734        {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */
 735        {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */
 736        {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */
 737        {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */
 738};
 739
 740const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
 741        {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_clk.vout1_clk */
 742        {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_de.vout1_de */
 743        {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
 744        {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
 745        {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d0.vout1_d0 */
 746        {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d1.vout1_d1 */
 747        {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d2.vout1_d2 */
 748        {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d3.vout1_d3 */
 749        {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d4.vout1_d4 */
 750        {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d5.vout1_d5 */
 751        {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d6.vout1_d6 */
 752        {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d7.vout1_d7 */
 753        {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d8.vout1_d8 */
 754        {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},    /* vout1_d9.vout1_d9 */
 755        {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d10.vout1_d10 */
 756        {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d11.vout1_d11 */
 757        {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d12.vout1_d12 */
 758        {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d13.vout1_d13 */
 759        {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d14.vout1_d14 */
 760        {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d15.vout1_d15 */
 761        {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d16.vout1_d16 */
 762        {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d17.vout1_d17 */
 763        {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d18.vout1_d18 */
 764        {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d19.vout1_d19 */
 765        {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d20.vout1_d20 */
 766        {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d21.vout1_d21 */
 767        {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d22.vout1_d22 */
 768        {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},   /* vout1_d23.vout1_d23 */
 769
 770        {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)},        /* mcasp5_aclkx.pr2_pru1_gpi1 */
 771        {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},  /* mcasp5_fsx.pr2_pru1_gpi2 */
 772        {UART2_RXD, (M0 | PIN_INPUT)},  /* uart2_rxd.uart2_rxd */
 773        {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
 774        {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},  /* vin2a_d5.pr1_pru1_gpo2 */
 775};
 776
 777const struct pad_conf_entry early_padconf[] = {
 778        {UART2_CTSN, (M2 | PIN_INPUT_SLEW)},    /* uart2_ctsn.uart3_rxd */
 779        {UART2_RTSN, (M1 | PIN_INPUT_SLEW)},    /* uart2_rtsn.uart3_txd */
 780        {I2C1_SDA, (PIN_INPUT_PULLUP | M0)},    /* I2C1_SDA */
 781        {I2C1_SCL, (PIN_INPUT_PULLUP | M0)},    /* I2C1_SCL */
 782};
 783
 784#ifdef CONFIG_IODELAY_RECALIBRATION
 785const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
 786        {0x0114, 2980, 0},      /* CFG_GPMC_A0_IN */
 787        {0x0120, 2648, 0},      /* CFG_GPMC_A10_IN */
 788        {0x012C, 2918, 0},      /* CFG_GPMC_A11_IN */
 789        {0x0198, 2917, 0},      /* CFG_GPMC_A1_IN */
 790        {0x0204, 3156, 178},    /* CFG_GPMC_A2_IN */
 791        {0x0210, 3109, 246},    /* CFG_GPMC_A3_IN */
 792        {0x021C, 3142, 100},    /* CFG_GPMC_A4_IN */
 793        {0x0228, 3084, 33},     /* CFG_GPMC_A5_IN */
 794        {0x0234, 2778, 0},      /* CFG_GPMC_A6_IN */
 795        {0x0240, 3110, 0},      /* CFG_GPMC_A7_IN */
 796        {0x024C, 2874, 0},      /* CFG_GPMC_A8_IN */
 797        {0x0258, 3072, 0},      /* CFG_GPMC_A9_IN */
 798        {0x0264, 2466, 0},      /* CFG_GPMC_AD0_IN */
 799        {0x0270, 2523, 0},      /* CFG_GPMC_AD10_IN */
 800        {0x027C, 2453, 0},      /* CFG_GPMC_AD11_IN */
 801        {0x0288, 2285, 0},      /* CFG_GPMC_AD12_IN */
 802        {0x0294, 2206, 0},      /* CFG_GPMC_AD13_IN */
 803        {0x02A0, 1898, 0},      /* CFG_GPMC_AD14_IN */
 804        {0x02AC, 2473, 0},      /* CFG_GPMC_AD15_IN */
 805        {0x02B8, 2307, 0},      /* CFG_GPMC_AD1_IN */
 806        {0x02C4, 2691, 0},      /* CFG_GPMC_AD2_IN */
 807        {0x02D0, 2384, 0},      /* CFG_GPMC_AD3_IN */
 808        {0x02DC, 2462, 0},      /* CFG_GPMC_AD4_IN */
 809        {0x02E8, 2335, 0},      /* CFG_GPMC_AD5_IN */
 810        {0x02F4, 2370, 0},      /* CFG_GPMC_AD6_IN */
 811        {0x0300, 2389, 0},      /* CFG_GPMC_AD7_IN */
 812        {0x030C, 2672, 0},      /* CFG_GPMC_AD8_IN */
 813        {0x0318, 2334, 0},      /* CFG_GPMC_AD9_IN */
 814        {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
 815        {0x0678, 406, 0},       /* CFG_MMC3_CLK_IN */
 816        {0x0680, 659, 0},       /* CFG_MMC3_CLK_OUT */
 817        {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
 818        {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
 819        {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
 820        {0x0690, 130, 0},       /* CFG_MMC3_DAT0_IN */
 821        {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
 822        {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
 823        {0x069C, 169, 0},       /* CFG_MMC3_DAT1_IN */
 824        {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
 825        {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
 826        {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
 827        {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
 828        {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
 829        {0x06B4, 457, 0},       /* CFG_MMC3_DAT3_IN */
 830        {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
 831        {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
 832        {0x06C0, 702, 0},       /* CFG_MMC3_DAT4_IN */
 833        {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
 834        {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
 835        {0x06CC, 738, 0},       /* CFG_MMC3_DAT5_IN */
 836        {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
 837        {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
 838        {0x06D8, 856, 0},       /* CFG_MMC3_DAT6_IN */
 839        {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
 840        {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
 841        {0x06E4, 610, 0},       /* CFG_MMC3_DAT7_IN */
 842        {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
 843        {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
 844        {0x06F0, 480, 0},       /* CFG_RGMII0_RXC_IN */
 845        {0x06FC, 111, 1641},    /* CFG_RGMII0_RXCTL_IN */
 846        {0x0708, 272, 1116},    /* CFG_RGMII0_RXD0_IN */
 847        {0x0714, 243, 1260},    /* CFG_RGMII0_RXD1_IN */
 848        {0x0720, 0, 1614},      /* CFG_RGMII0_RXD2_IN */
 849        {0x072C, 105, 1673},    /* CFG_RGMII0_RXD3_IN */
 850        {0x0740, 531, 120},     /* CFG_RGMII0_TXC_OUT */
 851        {0x074C, 201, 60},      /* CFG_RGMII0_TXCTL_OUT */
 852        {0x0758, 229, 120},     /* CFG_RGMII0_TXD0_OUT */
 853        {0x0764, 141, 0},       /* CFG_RGMII0_TXD1_OUT */
 854        {0x0770, 495, 120},     /* CFG_RGMII0_TXD2_OUT */
 855        {0x077C, 660, 120},     /* CFG_RGMII0_TXD3_OUT */
 856        {0x0A70, 1551, 115},    /* CFG_VIN2A_D12_OUT */
 857        {0x0A7C, 816, 0},       /* CFG_VIN2A_D13_OUT */
 858        {0x0A88, 876, 0},       /* CFG_VIN2A_D14_OUT */
 859        {0x0A94, 312, 0},       /* CFG_VIN2A_D15_OUT */
 860        {0x0AA0, 58, 0},        /* CFG_VIN2A_D16_OUT */
 861        {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
 862        {0x0AB0, 702, 0},       /* CFG_VIN2A_D18_IN */
 863        {0x0ABC, 136, 976},     /* CFG_VIN2A_D19_IN */
 864        {0x0AD4, 210, 1357},    /* CFG_VIN2A_D20_IN */
 865        {0x0AE0, 189, 1462},    /* CFG_VIN2A_D21_IN */
 866        {0x0AEC, 232, 1278},    /* CFG_VIN2A_D22_IN */
 867        {0x0AF8, 0, 1397},      /* CFG_VIN2A_D23_IN */
 868};
 869
 870const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
 871        {0x0114, 2519, 702},    /* CFG_GPMC_A0_IN */
 872        {0x0120, 2435, 411},    /* CFG_GPMC_A10_IN */
 873        {0x012C, 2379, 755},    /* CFG_GPMC_A11_IN */
 874        {0x0198, 2384, 778},    /* CFG_GPMC_A1_IN */
 875        {0x0204, 2499, 1127},   /* CFG_GPMC_A2_IN */
 876        {0x0210, 2455, 1181},   /* CFG_GPMC_A3_IN */
 877        {0x021C, 2486, 1039},   /* CFG_GPMC_A4_IN */
 878        {0x0228, 2456, 938},    /* CFG_GPMC_A5_IN */
 879        {0x0234, 2463, 573},    /* CFG_GPMC_A6_IN */
 880        {0x0240, 2608, 783},    /* CFG_GPMC_A7_IN */
 881        {0x024C, 2430, 656},    /* CFG_GPMC_A8_IN */
 882        {0x0258, 2465, 850},    /* CFG_GPMC_A9_IN */
 883        {0x0264, 2316, 301},    /* CFG_GPMC_AD0_IN */
 884        {0x0270, 2324, 406},    /* CFG_GPMC_AD10_IN */
 885        {0x027C, 2278, 352},    /* CFG_GPMC_AD11_IN */
 886        {0x0288, 2297, 160},    /* CFG_GPMC_AD12_IN */
 887        {0x0294, 2278, 108},    /* CFG_GPMC_AD13_IN */
 888        {0x02A0, 2035, 0},      /* CFG_GPMC_AD14_IN */
 889        {0x02AC, 2279, 378},    /* CFG_GPMC_AD15_IN */
 890        {0x02B8, 2440, 70},     /* CFG_GPMC_AD1_IN */
 891        {0x02C4, 2404, 446},    /* CFG_GPMC_AD2_IN */
 892        {0x02D0, 2343, 212},    /* CFG_GPMC_AD3_IN */
 893        {0x02DC, 2355, 322},    /* CFG_GPMC_AD4_IN */
 894        {0x02E8, 2337, 192},    /* CFG_GPMC_AD5_IN */
 895        {0x02F4, 2270, 314},    /* CFG_GPMC_AD6_IN */
 896        {0x0300, 2339, 259},    /* CFG_GPMC_AD7_IN */
 897        {0x030C, 2308, 577},    /* CFG_GPMC_AD8_IN */
 898        {0x0318, 2334, 166},    /* CFG_GPMC_AD9_IN */
 899        {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
 900        {0x0678, 0, 386},       /* CFG_MMC3_CLK_IN */
 901        {0x0680, 605, 0},       /* CFG_MMC3_CLK_OUT */
 902        {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
 903        {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
 904        {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
 905        {0x0690, 171, 0},       /* CFG_MMC3_DAT0_IN */
 906        {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
 907        {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
 908        {0x069C, 221, 0},       /* CFG_MMC3_DAT1_IN */
 909        {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
 910        {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
 911        {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
 912        {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
 913        {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
 914        {0x06B4, 474, 0},       /* CFG_MMC3_DAT3_IN */
 915        {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
 916        {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
 917        {0x06C0, 792, 0},       /* CFG_MMC3_DAT4_IN */
 918        {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
 919        {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
 920        {0x06CC, 782, 0},       /* CFG_MMC3_DAT5_IN */
 921        {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
 922        {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
 923        {0x06D8, 942, 0},       /* CFG_MMC3_DAT6_IN */
 924        {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
 925        {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
 926        {0x06E4, 636, 0},       /* CFG_MMC3_DAT7_IN */
 927        {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
 928        {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
 929        {0x06F0, 260, 0},       /* CFG_RGMII0_RXC_IN */
 930        {0x06FC, 0, 1412},      /* CFG_RGMII0_RXCTL_IN */
 931        {0x0708, 123, 1047},    /* CFG_RGMII0_RXD0_IN */
 932        {0x0714, 139, 1081},    /* CFG_RGMII0_RXD1_IN */
 933        {0x0720, 195, 1100},    /* CFG_RGMII0_RXD2_IN */
 934        {0x072C, 239, 1216},    /* CFG_RGMII0_RXD3_IN */
 935        {0x0740, 89, 0},        /* CFG_RGMII0_TXC_OUT */
 936        {0x074C, 15, 125},      /* CFG_RGMII0_TXCTL_OUT */
 937        {0x0758, 339, 162},     /* CFG_RGMII0_TXD0_OUT */
 938        {0x0764, 146, 94},      /* CFG_RGMII0_TXD1_OUT */
 939        {0x0770, 0, 27},        /* CFG_RGMII0_TXD2_OUT */
 940        {0x077C, 291, 205},     /* CFG_RGMII0_TXD3_OUT */
 941        {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
 942        {0x0A7C, 219, 101},     /* CFG_VIN2A_D13_OUT */
 943        {0x0A88, 92, 58},       /* CFG_VIN2A_D14_OUT */
 944        {0x0A94, 135, 100},     /* CFG_VIN2A_D15_OUT */
 945        {0x0AA0, 154, 101},     /* CFG_VIN2A_D16_OUT */
 946        {0x0AAC, 78, 27},       /* CFG_VIN2A_D17_OUT */
 947        {0x0AB0, 411, 0},       /* CFG_VIN2A_D18_IN */
 948        {0x0ABC, 0, 382},       /* CFG_VIN2A_D19_IN */
 949        {0x0AD4, 320, 750},     /* CFG_VIN2A_D20_IN */
 950        {0x0AE0, 192, 836},     /* CFG_VIN2A_D21_IN */
 951        {0x0AEC, 294, 669},     /* CFG_VIN2A_D22_IN */
 952        {0x0AF8, 50, 700},      /* CFG_VIN2A_D23_IN */
 953        {0x0B9C, 0, 706},       /* CFG_VOUT1_CLK_OUT */
 954        {0x0BA8, 2313, 0},      /* CFG_VOUT1_D0_OUT */
 955        {0x0BB4, 2199, 0},      /* CFG_VOUT1_D10_OUT */
 956        {0x0BC0, 2266, 0},      /* CFG_VOUT1_D11_OUT */
 957        {0x0BCC, 3159, 0},      /* CFG_VOUT1_D12_OUT */
 958        {0x0BD8, 2100, 0},      /* CFG_VOUT1_D13_OUT */
 959        {0x0BE4, 2229, 0},      /* CFG_VOUT1_D14_OUT */
 960        {0x0BF0, 2202, 0},      /* CFG_VOUT1_D15_OUT */
 961        {0x0BFC, 2084, 0},      /* CFG_VOUT1_D16_OUT */
 962        {0x0C08, 2195, 0},      /* CFG_VOUT1_D17_OUT */
 963        {0x0C14, 2342, 0},      /* CFG_VOUT1_D18_OUT */
 964        {0x0C20, 2463, 0},      /* CFG_VOUT1_D19_OUT */
 965        {0x0C2C, 2439, 0},      /* CFG_VOUT1_D1_OUT */
 966        {0x0C38, 2304, 0},      /* CFG_VOUT1_D20_OUT */
 967        {0x0C44, 2103, 0},      /* CFG_VOUT1_D21_OUT */
 968        {0x0C50, 2145, 0},      /* CFG_VOUT1_D22_OUT */
 969        {0x0C5C, 1932, 0},      /* CFG_VOUT1_D23_OUT */
 970        {0x0C68, 2200, 0},      /* CFG_VOUT1_D2_OUT */
 971        {0x0C74, 2355, 0},      /* CFG_VOUT1_D3_OUT */
 972        {0x0C80, 3215, 0},      /* CFG_VOUT1_D4_OUT */
 973        {0x0C8C, 2314, 0},      /* CFG_VOUT1_D5_OUT */
 974        {0x0C98, 2238, 0},      /* CFG_VOUT1_D6_OUT */
 975        {0x0CA4, 2381, 0},      /* CFG_VOUT1_D7_OUT */
 976        {0x0CB0, 2138, 0},      /* CFG_VOUT1_D8_OUT */
 977        {0x0CBC, 2383, 0},      /* CFG_VOUT1_D9_OUT */
 978        {0x0CC8, 1984, 0},      /* CFG_VOUT1_DE_OUT */
 979        {0x0CE0, 1947, 0},      /* CFG_VOUT1_HSYNC_OUT */
 980        {0x0CEC, 2739, 0},      /* CFG_VOUT1_VSYNC_OUT */
 981};
 982
 983const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
 984        {0x0114, 1861, 901},    /* CFG_GPMC_A0_IN */
 985        {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
 986        {0x012C, 1783, 1178},   /* CFG_GPMC_A11_IN */
 987        {0x0138, 1903, 853},    /* CFG_GPMC_A12_IN */
 988        {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
 989        {0x0150, 2575, 966},    /* CFG_GPMC_A14_IN */
 990        {0x015C, 2503, 889},    /* CFG_GPMC_A15_IN */
 991        {0x0168, 2528, 1007},   /* CFG_GPMC_A16_IN */
 992        {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
 993        {0x0174, 2533, 980},    /* CFG_GPMC_A17_IN */
 994        {0x0188, 590, 0},       /* CFG_GPMC_A18_OUT */
 995        {0x0198, 1652, 891},    /* CFG_GPMC_A1_IN */
 996        {0x0204, 1888, 1212},   /* CFG_GPMC_A2_IN */
 997        {0x0210, 1839, 1274},   /* CFG_GPMC_A3_IN */
 998        {0x021C, 1868, 1113},   /* CFG_GPMC_A4_IN */
 999        {0x0228, 1757, 1079},   /* CFG_GPMC_A5_IN */
1000        {0x0234, 1800, 670},    /* CFG_GPMC_A6_IN */

1001        {0x0240, 1967, 898},    /* CFG_GPMC_A7_IN */
1002        {0x024C, 1731, 959},    /* CFG_GPMC_A8_IN */
1003        {0x0258, 1766, 1150},   /* CFG_GPMC_A9_IN */
1004        {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1005        {0x0590, 1000, 4200},   /* CFG_MCASP5_ACLKX_OUT */
1006        {0x05AC, 800, 3800},    /* CFG_MCASP5_FSX_IN */
1007        {0x06F0, 260, 0},       /* CFG_RGMII0_RXC_IN */
1008        {0x06FC, 0, 1412},      /* CFG_RGMII0_RXCTL_IN */
1009        {0x0708, 123, 1047},    /* CFG_RGMII0_RXD0_IN */
1010        {0x0714, 139, 1081},    /* CFG_RGMII0_RXD1_IN */
1011        {0x0720, 195, 1100},    /* CFG_RGMII0_RXD2_IN */
1012        {0x072C, 239, 1216},    /* CFG_RGMII0_RXD3_IN */
1013        {0x0740, 89, 0},        /* CFG_RGMII0_TXC_OUT */
1014        {0x074C, 15, 125},      /* CFG_RGMII0_TXCTL_OUT */
1015        {0x0758, 339, 162},     /* CFG_RGMII0_TXD0_OUT */
1016        {0x0764, 146, 94},      /* CFG_RGMII0_TXD1_OUT */
1017        {0x0770, 0, 27},        /* CFG_RGMII0_TXD2_OUT */
1018        {0x077C, 291, 205},     /* CFG_RGMII0_TXD3_OUT */
1019        {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1020        {0x0A7C, 219, 101},     /* CFG_VIN2A_D13_OUT */
1021        {0x0A88, 92, 58},       /* CFG_VIN2A_D14_OUT */
1022        {0x0A94, 135, 100},     /* CFG_VIN2A_D15_OUT */
1023        {0x0AA0, 154, 101},     /* CFG_VIN2A_D16_OUT */
1024        {0x0AAC, 78, 27},       /* CFG_VIN2A_D17_OUT */
1025        {0x0AB0, 411, 0},       /* CFG_VIN2A_D18_IN */
1026        {0x0ABC, 0, 382},       /* CFG_VIN2A_D19_IN */
1027        {0x0AD4, 320, 750},     /* CFG_VIN2A_D20_IN */
1028        {0x0AE0, 192, 836},     /* CFG_VIN2A_D21_IN */
1029        {0x0AEC, 294, 669},     /* CFG_VIN2A_D22_IN */
1030        {0x0AF8, 50, 700},      /* CFG_VIN2A_D23_IN */
1031        {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
1032        {0x0B9C, 1126, 751},    /* CFG_VOUT1_CLK_OUT */
1033        {0x0BA8, 395, 0},       /* CFG_VOUT1_D0_OUT */
1034        {0x0BB4, 282, 0},       /* CFG_VOUT1_D10_OUT */
1035        {0x0BC0, 348, 0},       /* CFG_VOUT1_D11_OUT */
1036        {0x0BCC, 1240, 0},      /* CFG_VOUT1_D12_OUT */
1037        {0x0BD8, 182, 0},       /* CFG_VOUT1_D13_OUT */
1038        {0x0BE4, 311, 0},       /* CFG_VOUT1_D14_OUT */
1039        {0x0BF0, 285, 0},       /* CFG_VOUT1_D15_OUT */
1040        {0x0BFC, 166, 0},       /* CFG_VOUT1_D16_OUT */
1041        {0x0C08, 278, 0},       /* CFG_VOUT1_D17_OUT */
1042        {0x0C14, 425, 0},       /* CFG_VOUT1_D18_OUT */
1043        {0x0C20, 516, 0},       /* CFG_VOUT1_D19_OUT */
1044        {0x0C2C, 521, 0},       /* CFG_VOUT1_D1_OUT */
1045        {0x0C38, 386, 0},       /* CFG_VOUT1_D20_OUT */
1046        {0x0C44, 111, 0},       /* CFG_VOUT1_D21_OUT */
1047        {0x0C50, 227, 0},       /* CFG_VOUT1_D22_OUT */
1048        {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */
1049        {0x0C68, 282, 0},       /* CFG_VOUT1_D2_OUT */
1050        {0x0C74, 438, 0},       /* CFG_VOUT1_D3_OUT */
1051        {0x0C80, 1298, 0},      /* CFG_VOUT1_D4_OUT */
1052        {0x0C8C, 397, 0},       /* CFG_VOUT1_D5_OUT */
1053        {0x0C98, 321, 0},       /* CFG_VOUT1_D6_OUT */
1054        {0x0CA4, 155, 309},     /* CFG_VOUT1_D7_OUT */
1055        {0x0CB0, 212, 0},       /* CFG_VOUT1_D8_OUT */
1056        {0x0CBC, 466, 0},       /* CFG_VOUT1_D9_OUT */
1057        {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1058        {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1059        {0x0CEC, 139, 701},     /* CFG_VOUT1_VSYNC_OUT */
1060};
1061
1062const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
1063        {0x0114, 1873, 702},    /* CFG_GPMC_A0_IN */
1064        {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1065        {0x012C, 1851, 1011},   /* CFG_GPMC_A11_IN */
1066        {0x0138, 2009, 601},    /* CFG_GPMC_A12_IN */
1067        {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1068        {0x0150, 2247, 1186},   /* CFG_GPMC_A14_IN */
1069        {0x015C, 2176, 1197},   /* CFG_GPMC_A15_IN */
1070        {0x0168, 2229, 1268},   /* CFG_GPMC_A16_IN */
1071        {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1072        {0x0174, 2251, 1217},   /* CFG_GPMC_A17_IN */
1073        {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1074        {0x0198, 1629, 772},    /* CFG_GPMC_A1_IN */
1075        {0x0204, 1734, 898},    /* CFG_GPMC_A2_IN */
1076        {0x0210, 1757, 1076},   /* CFG_GPMC_A3_IN */
1077        {0x021C, 1794, 893},    /* CFG_GPMC_A4_IN */
1078        {0x0228, 1726, 853},    /* CFG_GPMC_A5_IN */
1079        {0x0234, 1792, 612},    /* CFG_GPMC_A6_IN */
1080        {0x0240, 2117, 610},    /* CFG_GPMC_A7_IN */
1081        {0x024C, 1758, 653},    /* CFG_GPMC_A8_IN */
1082        {0x0258, 1705, 899},    /* CFG_GPMC_A9_IN */
1083        {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1084        {0x06F0, 413, 0},       /* CFG_RGMII0_RXC_IN */
1085        {0x06FC, 27, 2296},     /* CFG_RGMII0_RXCTL_IN */
1086        {0x0708, 3, 1721},      /* CFG_RGMII0_RXD0_IN */
1087        {0x0714, 134, 1786},    /* CFG_RGMII0_RXD1_IN */
1088        {0x0720, 40, 1966},     /* CFG_RGMII0_RXD2_IN */
1089        {0x072C, 0, 2057},      /* CFG_RGMII0_RXD3_IN */
1090        {0x0740, 0, 60},        /* CFG_RGMII0_TXC_OUT */
1091        {0x074C, 0, 60},        /* CFG_RGMII0_TXCTL_OUT */
1092        {0x0758, 0, 60},        /* CFG_RGMII0_TXD0_OUT */
1093        {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
1094        {0x0770, 0, 60},        /* CFG_RGMII0_TXD2_OUT */
1095        {0x077C, 0, 120},       /* CFG_RGMII0_TXD3_OUT */
1096        {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1097        {0x0A7C, 170, 0},       /* CFG_VIN2A_D13_OUT */
1098        {0x0A88, 150, 0},       /* CFG_VIN2A_D14_OUT */
1099        {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
1100        {0x0AA0, 60, 0},        /* CFG_VIN2A_D16_OUT */
1101        {0x0AAC, 60, 0},        /* CFG_VIN2A_D17_OUT */
1102        {0x0AB0, 530, 0},       /* CFG_VIN2A_D18_IN */
1103        {0x0ABC, 71, 1099},     /* CFG_VIN2A_D19_IN */
1104        {0x0AD4, 142, 1337},    /* CFG_VIN2A_D20_IN */
1105        {0x0AE0, 114, 1517},    /* CFG_VIN2A_D21_IN */
1106        {0x0AEC, 171, 1331},    /* CFG_VIN2A_D22_IN */
1107        {0x0AF8, 0, 1328},      /* CFG_VIN2A_D23_IN */
1108};
1109
1110const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
1111        {0x0588, 2100, 1959},   /* CFG_MCASP5_ACLKX_IN */
1112        {0x05AC, 2100, 1780},   /* CFG_MCASP5_FSX_IN */
1113        {0x0B30, 0, 400},       /* CFG_VIN2A_D5_OUT */
1114};
1115#endif
1116#endif /* _MUX_DATA_BEAGLE_X15_H_ */
1117