LXR uboot/drivers/ddr/marvell/a38x/ddr3

   1/*
   2 * Copyright (C) Marvell International Ltd. and its affiliates
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0
   5 */
   6
   7#ifndef _DDR3_A38X_H
   8#define _DDR3_A38X_H
   9
  10#define MAX_INTERFACE_NUM               1
  11#define MAX_BUS_NUM                     5
  12
  13#include "ddr3_hws_hw_training_def.h"
  14
  15#define ECC_SUPPORT
  16
  17/* right now, we're not supporting this in mainline */
  18#undef SUPPORT_STATIC_DUNIT_CONFIG
  19
  20/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
  21#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER     1
  22
  23/* Tune internal training params values */
  24#define TUNE_TRAINING_PARAMS_CK_DELAY           160
  25#define TUNE_TRAINING_PARAMS_CK_DELAY_16        160
  26#define TUNE_TRAINING_PARAMS_PFINGER            41
  27#define TUNE_TRAINING_PARAMS_NFINGER            43
  28#define TUNE_TRAINING_PARAMS_PHYREG3VAL         0xa
  29
  30#define MARVELL_BOARD                           MARVELL_BOARD_ID_BASE
  31
  32
  33#define REG_DEVICE_SAR1_ADDR                    0xe4204
  34#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET     17
  35#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK       0x1f
  36
  37/* DRAM Windows */
  38#define REG_XBAR_WIN_5_CTRL_ADDR                0x20050
  39#define REG_XBAR_WIN_5_BASE_ADDR                0x20054
  40
  41/* DRAM Windows */
  42#define REG_XBAR_WIN_4_CTRL_ADDR                0x20040
  43#define REG_XBAR_WIN_4_BASE_ADDR                0x20044
  44#define REG_XBAR_WIN_4_REMAP_ADDR               0x20048
  45#define REG_XBAR_WIN_7_REMAP_ADDR               0x20078
  46#define REG_XBAR_WIN_16_CTRL_ADDR               0x200d0
  47#define REG_XBAR_WIN_16_BASE_ADDR               0x200d4
  48#define REG_XBAR_WIN_16_REMAP_ADDR              0x200dc
  49#define REG_XBAR_WIN_19_CTRL_ADDR               0x200e8
  50
  51#define REG_FASTPATH_WIN_BASE_ADDR(win)         (0x20180 + (0x8 * win))
  52#define REG_FASTPATH_WIN_CTRL_ADDR(win)         (0x20184 + (0x8 * win))
  53
  54/* SatR defined too change topology busWidth and ECC configuration */
  55#define DDR_SATR_CONFIG_MASK_WIDTH              0x8
  56#define DDR_SATR_CONFIG_MASK_ECC                0x10
  57#define DDR_SATR_CONFIG_MASK_ECC_PUP            0x20
  58
  59#define REG_SAMPLE_RESET_HIGH_ADDR              0x18600
  60
  61#define MV_BOARD_REFCLK                         MV_BOARD_REFCLK_25MHZ
  62
  63/* Matrix enables DRAM modes (bus width/ECC) per boardId */
  64#define TOPOLOGY_UPDATE_32BIT                   0
  65#define TOPOLOGY_UPDATE_32BIT_ECC               1
  66#define TOPOLOGY_UPDATE_16BIT                   2
  67#define TOPOLOGY_UPDATE_16BIT_ECC               3
  68#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3          4
  69#define TOPOLOGY_UPDATE { \
  70                /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
  71                {1, 1, 1, 1, 1},        /* RD_NAS_68XX_ID */ \
  72                {1, 1, 1, 1, 1},        /* DB_68XX_ID     */ \
  73                {1, 0, 1, 0, 1},        /* RD_AP_68XX_ID  */ \
  74                {1, 0, 1, 0, 1},        /* DB_AP_68XX_ID  */ \
  75                {1, 0, 1, 0, 1},        /* DB_GP_68XX_ID  */ \
  76                {0, 0, 1, 1, 0},        /* DB_BP_6821_ID  */ \
  77                {1, 1, 1, 1, 1}         /* DB_AMC_6820_ID */ \
  78        };
  79
  80enum {
  81        CPU_1066MHZ_DDR_400MHZ,
  82        CPU_RESERVED_DDR_RESERVED0,
  83        CPU_667MHZ_DDR_667MHZ,
  84        CPU_800MHZ_DDR_800MHZ,
  85        CPU_RESERVED_DDR_RESERVED1,
  86        CPU_RESERVED_DDR_RESERVED2,
  87        CPU_RESERVED_DDR_RESERVED3,
  88        LAST_FREQ
  89};
  90
  91#define ACTIVE_INTERFACE_MASK                   0x1
  92
  93#endif /* _DDR3_A38X_H */
  94