uboot/drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h
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   1/*
   2 * Copyright (C) Marvell International Ltd. and its affiliates
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0
   5 */
   6
   7#ifndef _DDR3_A38X_MC_STATIC_H
   8#define _DDR3_A38X_MC_STATIC_H
   9
  10#include "ddr3_a38x.h"
  11
  12#ifdef SUPPORT_STATIC_DUNIT_CONFIG
  13
  14#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
  15static struct reg_data ddr3_customer_800[] = {
  16        /* parameters for customer board (based on 800MHZ) */
  17        {0x1400,        0x7b00cc30, 0xffffffff},
  18        {0x1404,        0x36301820, 0xffffffff},
  19        {0x1408,        0x5415baab, 0xffffffff},
  20        {0x140c,        0x38411def, 0xffffffff},
  21        {0x1410,        0x18300000, 0xffffffff},
  22        {0x1414,        0x00000700, 0xffffffff},
  23        {0x1424,        0x0060f3ff, 0xffffffff},
  24        {0x1428,        0x0011a940, 0xffffffff},
  25        {0x142c,        0x28c5134,  0xffffffff},
  26        {0x1474,        0x00000000, 0xffffffff},
  27        {0x147c,        0x0000d771, 0xffffffff},
  28        {0x1494,        0x00030000, 0xffffffff},
  29        {0x149c,        0x00000300, 0xffffffff},
  30        {0x14a8,        0x00000000, 0xffffffff},
  31        {0x14cc,        0xbd09000d, 0xffffffff},
  32        {0x1504,        0xfffffff1, 0xffffffff},
  33        {0x150c,        0xffffffe5, 0xffffffff},
  34        {0x1514,        0x00000000, 0xffffffff},
  35        {0x151c,        0x00000000, 0xffffffff},
  36        {0x1538,        0x00000b0b, 0xffffffff},
  37        {0x153c,        0x00000c0c, 0xffffffff},
  38        {0x15d0,        0x00000670, 0xffffffff},
  39        {0x15d4,        0x00000046, 0xffffffff},
  40        {0x15d8,        0x00000010, 0xffffffff},
  41        {0x15dc,        0x00000000, 0xffffffff},
  42        {0x15e0,        0x00000023, 0xffffffff},
  43        {0x15e4,        0x00203c18, 0xffffffff},
  44        {0x15ec,        0xf8000019, 0xffffffff},
  45        {0x16a0,        0xcc000006, 0xffffffff},        /* Clock Delay */
  46        {0xe4124,       0x08008073, 0xffffffff},        /* AVS BG default */
  47        {0, 0, 0}
  48};
  49
  50#else /* CONFIG_CUSTOMER_BOARD_SUPPORT */
  51
  52struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = {
  53        /* parameters for 933MHZ */
  54        {0x1400,        0x7b00ce3a, 0xffffffff},
  55        {0x1404,        0x36301820, 0xffffffff},
  56        {0x1408,        0x7417eccf, 0xffffffff},
  57        {0x140c,        0x3e421f98, 0xffffffff},
  58        {0x1410,        0x1a300000, 0xffffffff},
  59        {0x1414,        0x00000700, 0xffffffff},
  60        {0x1424,        0x0060f3ff, 0xffffffff},
  61        {0x1428,        0x0013ca50, 0xffffffff},
  62        {0x142c,        0x028c5165, 0xffffffff},
  63        {0x1474,        0x00000000, 0xffffffff},
  64        {0x147c,        0x0000e871, 0xffffffff},
  65        {0x1494,        0x00010000, 0xffffffff},
  66        {0x149c,        0x00000001, 0xffffffff},
  67        {0x14a8,        0x00000000, 0xffffffff},
  68        {0x14cc,        0xbd09000d, 0xffffffff},
  69        {0x1504,        0xffffffe1, 0xffffffff},
  70        {0x150c,        0xffffffe5, 0xffffffff},
  71        {0x1514,        0x00000000, 0xffffffff},
  72        {0x151c,        0x00000000, 0xffffffff},
  73        {0x1538,        0x00000d0d, 0xffffffff},
  74        {0x153c,        0x00000d0d, 0xffffffff},
  75        {0x15d0,        0x00000608, 0xffffffff},
  76        {0x15d4,        0x00000044, 0xffffffff},
  77        {0x15d8,        0x00000020, 0xffffffff},
  78        {0x15dc,        0x00000000, 0xffffffff},
  79        {0x15e0,        0x00000021, 0xffffffff},
  80        {0x15e4,        0x00203c18, 0xffffffff},
  81        {0x15ec,        0xf8000019, 0xffffffff},
  82        {0x16a0,        0xcc000006, 0xffffffff},        /* Clock Delay */
  83        {0xe4124,       0x08008073, 0xffffffff},        /* AVS BG default */
  84        {0, 0, 0}
  85};
  86
  87static struct reg_data ddr3_a38x_800[] = {
  88        /* parameters for 800MHZ */
  89        {0x1400,        0x7b00cc30, 0xffffffff},
  90        {0x1404,        0x36301820, 0xffffffff},
  91        {0x1408,        0x5415baab, 0xffffffff},
  92        {0x140c,        0x38411def, 0xffffffff},
  93        {0x1410,        0x18300000, 0xffffffff},
  94        {0x1414,        0x00000700, 0xffffffff},
  95        {0x1424,        0x0060f3ff, 0xffffffff},
  96        {0x1428,        0x0011a940, 0xffffffff},
  97        {0x142c,        0x28c5134,  0xffffffff},
  98        {0x1474,        0x00000000, 0xffffffff},
  99        {0x147c,        0x0000d771, 0xffffffff},
 100        {0x1494,        0x00030000, 0xffffffff},
 101        {0x149c,        0x00000300, 0xffffffff},
 102        {0x14a8,        0x00000000, 0xffffffff},
 103        {0x14cc,        0xbd09000d, 0xffffffff},
 104        {0x1504,        0xfffffff1, 0xffffffff},
 105        {0x150c,        0xffffffe5, 0xffffffff},
 106        {0x1514,        0x00000000, 0xffffffff},
 107        {0x151c,        0x00000000, 0xffffffff},
 108        {0x1538,        0x00000b0b, 0xffffffff},
 109        {0x153c,        0x00000c0c, 0xffffffff},
 110        {0x15d0,        0x00000670, 0xffffffff},
 111        {0x15d4,        0x00000046, 0xffffffff},
 112        {0x15d8,        0x00000010, 0xffffffff},
 113        {0x15dc,        0x00000000, 0xffffffff},
 114        {0x15e0,        0x00000023, 0xffffffff},
 115        {0x15e4,        0x00203c18, 0xffffffff},
 116        {0x15ec,        0xf8000019, 0xffffffff},
 117        {0x16a0,        0xcc000006, 0xffffffff},        /* Clock Delay */
 118        {0xe4124,       0x08008073, 0xffffffff},        /* AVS BG default */
 119        {0,   0, 0}
 120};
 121
 122static struct reg_data ddr3_a38x_667[] = {
 123        /* parameters for 667MHZ */
 124        /* DDR SDRAM Configuration Register */
 125        {0x1400,    0x7b00ca28, 0xffffffff},
 126        /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
 127        {0x1404,    0x36301820, 0xffffffff},
 128        /* DDR SDRAM Timing (Low) Register */
 129        {0x1408,    0x43149997, 0xffffffff},
 130        /* DDR SDRAM Timing (High) Register */
 131        {0x140c,    0x38411bc7, 0xffffffff},
 132        /* DDR SDRAM Address Control Register */
 133        {0x1410,    0x14330000, 0xffffffff},
 134        /* DDR SDRAM Open Pages Control Register */
 135        {0x1414,    0x00000700, 0xffffffff},
 136        /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
 137        {0x1424,    0x0060f3ff, 0xffffffff},
 138        /* Dunit Control High Register */
 139        {0x1428,    0x000f8830, 0xffffffff},
 140        /* Dunit Control High Register  (2:1 -  bit 29 = '1') */
 141        {0x142c,    0x28c50f8,  0xffffffff},
 142        {0x147c,    0x0000c671, 0xffffffff},
 143        /* DDR SDRAM ODT Control (Low) Register */
 144        {0x1494,    0x00030000, 0xffffffff},
 145        /* DDR SDRAM ODT Control (High) Register, will be configured at WL */
 146        {0x1498,    0x00000000, 0xffffffff},
 147        /* DDR Dunit ODT Control Register */
 148        {0x149c,    0x00000300, 0xffffffff},
 149        {0x14a8,    0x00000000, 0xffffffff}, /*  */
 150        {0x14cc,    0xbd09000d, 0xffffffff}, /*  */
 151        {0x1474,    0x00000000, 0xffffffff},
 152        /* Read Data Sample Delays Register */
 153        {0x1538,    0x00000009, 0xffffffff},
 154        /* Read Data Ready Delay Register */
 155        {0x153c,    0x0000000c, 0xffffffff},
 156        {0x1504,    0xfffffff1, 0xffffffff}, /*  */
 157        {0x150c,    0xffffffe5, 0xffffffff}, /*  */
 158        {0x1514,    0x00000000, 0xffffffff}, /*  */
 159        {0x151c,    0x0,        0xffffffff}, /*  */
 160        {0x15d0,    0x00000650, 0xffffffff}, /* MR0 */
 161        {0x15d4,    0x00000046, 0xffffffff}, /* MR1 */
 162        {0x15d8,    0x00000010, 0xffffffff}, /* MR2 */
 163        {0x15dc,    0x00000000, 0xffffffff}, /* MR3 */
 164        {0x15e0,    0x23,       0xffffffff}, /*  */
 165        {0x15e4,    0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
 166        {0x15ec,    0xf8000019, 0xffffffff}, /* DDR PHY */
 167        {0x16a0,    0xcc000006, 0xffffffff}, /* Clock Delay */
 168        {0xe4124,   0x08008073, 0xffffffff}, /* AVS BG default */
 169        {0, 0, 0}
 170};
 171
 172static struct reg_data ddr3_a38x_533[] = {
 173        /* parameters for 533MHZ */
 174        /* DDR SDRAM Configuration Register */
 175        {0x1400,    0x7b00d040, 0xffffffff},
 176        /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
 177        {0x1404,    0x36301820, 0xffffffff},
 178        /* DDR SDRAM Timing (Low) Register */
 179        {0x1408,    0x33137772, 0xffffffff},
 180        /* DDR SDRAM Timing (High) Register */
 181        {0x140c,    0x3841199f, 0xffffffff},
 182        /* DDR SDRAM Address Control Register */
 183        {0x1410,    0x10330000, 0xffffffff},
 184        /* DDR SDRAM Open Pages Control Register */
 185        {0x1414,    0x00000700, 0xffffffff},
 186        /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
 187        {0x1424,    0x0060f3ff, 0xffffffff},
 188        /* Dunit Control High Register */
 189        {0x1428,    0x000d6720, 0xffffffff},
 190        /* Dunit Control High Register  (2:1 -  bit 29 = '1') */
 191        {0x142c,    0x028c50c3, 0xffffffff},
 192        {0x147c,    0x0000b571, 0xffffffff},
 193        /* DDR SDRAM ODT Control (Low) Register */
 194        {0x1494,    0x00030000, 0xffffffff},
 195        /* DDR SDRAM ODT Control (High) Register, will be configured at WL */
 196        {0x1498,    0x00000000, 0xffffffff},
 197        /* DDR Dunit ODT Control Register */
 198        {0x149c,    0x00000003, 0xffffffff},
 199        {0x14a8,    0x00000000, 0xffffffff}, /*  */
 200        {0x14cc,    0xbd09000d, 0xffffffff}, /*  */
 201        {0x1474,    0x00000000, 0xffffffff},
 202        /* Read Data Sample Delays Register */
 203        {0x1538,    0x00000707, 0xffffffff},
 204        /* Read Data Ready Delay Register */
 205        {0x153c,    0x00000707, 0xffffffff},
 206        {0x1504,    0xffffffe1, 0xffffffff}, /*  */
 207        {0x150c,    0xffffffe5, 0xffffffff}, /*  */
 208        {0x1514,    0x00000000, 0xffffffff}, /*  */
 209        {0x151c,    0x00000000, 0xffffffff}, /*  */
 210        {0x15d0,    0x00000630, 0xffffffff}, /* MR0 */
 211        {0x15d4,    0x00000046, 0xffffffff}, /* MR1 */
 212        {0x15d8,    0x00000008, 0xffffffff}, /* MR2 */
 213        {0x15dc,    0x00000000, 0xffffffff}, /* MR3 */
 214        {0x15e0,    0x00000023, 0xffffffff}, /*  */
 215        {0x15e4,    0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
 216        {0x15ec,    0xf8000019, 0xffffffff}, /* DDR PHY */
 217        {0x16a0,    0xcc000006, 0xffffffff}, /* Clock Delay */
 218        {0xe4124,   0x08008073, 0xffffffff}, /* AVS BG default */
 219        {0, 0, 0}
 220};
 221
 222#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
 223
 224#endif /* SUPPORT_STATIC_DUNIT_CONFIG */
 225
 226#endif /* _DDR3_A38X_MC_STATIC_H */
 227
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