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7#ifndef _DDR3_TRAINING_IP_ENGINE_H_
8#define _DDR3_TRAINING_IP_ENGINE_H_
9
10#include "ddr3_training_ip_def.h"
11#include "ddr3_training_ip_flow.h"
12
13#define EDGE_1 0
14#define EDGE_2 1
15#define ALL_PUP_TRAINING 0xe
16#define PUP_RESULT_EDGE_1_MASK 0xff
17#define PUP_RESULT_EDGE_2_MASK (0xff << 8)
18#define PUP_LOCK_RESULT_BIT 25
19
20#define GET_TAP_RESULT(reg, edge) \
21 (((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
22 (((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
23#define GET_LOCK_RESULT(reg) \
24 (((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
25
26#define EDGE_FAILURE 128
27#define ALL_BITS_PER_PUP 128
28
29#define MIN_WINDOW_SIZE 6
30#define MAX_WINDOW_SIZE_RX 32
31#define MAX_WINDOW_SIZE_TX 64
32
33int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
34 enum hws_search_dir search_dir,
35 enum hws_dir direction,
36 enum hws_edge_compare edge,
37 u32 init_val1, u32 init_val2,
38 u32 num_of_iterations, u32 start_pattern,
39 u32 end_pattern);
40int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
41int ddr3_tip_load_pattern_to_mem_by_cpu(u32 dev_num, enum hws_pattern pattern,
42 u32 offset);
43int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
44int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
45 enum hws_access_type pup_access_type,
46 u32 pup_num, u32 bit_num,
47 enum hws_search_dir search,
48 enum hws_dir direction,
49 enum hws_training_result result_type,
50 enum hws_training_load_op operation,
51 u32 cs_num_type, u32 **load_res,
52 int is_read_from_db, u8 cons_tap,
53 int is_check_result_validity);
54int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
55 u32 interface_num,
56 enum hws_access_type pup_access_type,
57 u32 pup_num, enum hws_training_result result_type,
58 enum hws_control_element control_element,
59 enum hws_search_dir search_dir, enum hws_dir direction,
60 u32 interface_mask, u32 init_value, u32 num_iter,
61 enum hws_pattern pattern,
62 enum hws_edge_compare edge_comp,
63 enum hws_ddr_cs cs_type, u32 cs_num,
64 enum hws_training_ip_stat *train_status);
65int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
66 u32 if_id,
67 enum hws_access_type pup_access_type,
68 u32 pup_num,
69 enum hws_training_result result_type,
70 enum hws_control_element control_element,
71 enum hws_search_dir search_dir,
72 enum hws_dir direction,
73 u32 interface_mask, u32 init_value1,
74 u32 init_value2, u32 num_iter,
75 enum hws_pattern pattern,
76 enum hws_edge_compare edge_comp,
77 enum hws_ddr_cs train_cs_type, u32 cs_num,
78 enum hws_training_ip_stat *train_status);
79int is_odpg_access_done(u32 dev_num, u32 if_id);
80void ddr3_tip_print_bist_res(void);
81struct pattern_info *ddr3_tip_get_pattern_table(void);
82u16 *ddr3_tip_get_mask_results_dq_reg(void);
83u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
84
85#endif
86
