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10#include <config.h>
11#include <common.h>
12#include <command.h>
13#include <dm.h>
14#include <dm/device-internal.h>
15#include <errno.h>
16#include <mmc.h>
17#include <part.h>
18#include <power/regulator.h>
19#include <malloc.h>
20#include <memalign.h>
21#include <linux/list.h>
22#include <div64.h>
23#include "mmc_private.h"
24
25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
33#if CONFIG_IS_ENABLED(MMC_TINY)
34static struct mmc mmc_static;
35struct mmc *find_mmc_device(int dev_num)
36{
37 return &mmc_static;
38}
39
40void mmc_do_preinit(void)
41{
42 struct mmc *m = &mmc_static;
43#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
45#endif
46 if (m->preinit)
47 mmc_start_init(m);
48}
49
50struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
51{
52 return &mmc->block_dev;
53}
54#endif
55
56#if !CONFIG_IS_ENABLED(DM_MMC)
57__weak int board_mmc_getwp(struct mmc *mmc)
58{
59 return -1;
60}
61
62int mmc_getwp(struct mmc *mmc)
63{
64 int wp;
65
66 wp = board_mmc_getwp(mmc);
67
68 if (wp < 0) {
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
71 else
72 wp = 0;
73 }
74
75 return wp;
76}
77
78__weak int board_mmc_getcd(struct mmc *mmc)
79{
80 return -1;
81}
82#endif
83
84#ifdef CONFIG_MMC_TRACE
85void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
86{
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
89}
90
91void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
92{
93 int i;
94 u8 *ptr;
95
96 if (ret) {
97 printf("\t\tRET\t\t\t %d\n", ret);
98 } else {
99 switch (cmd->resp_type) {
100 case MMC_RSP_NONE:
101 printf("\t\tMMC_RSP_NONE\n");
102 break;
103 case MMC_RSP_R1:
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
105 cmd->response[0]);
106 break;
107 case MMC_RSP_R1b:
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
109 cmd->response[0]);
110 break;
111 case MMC_RSP_R2:
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
113 cmd->response[0]);
114 printf("\t\t \t\t 0x%08X \n",
115 cmd->response[1]);
116 printf("\t\t \t\t 0x%08X \n",
117 cmd->response[2]);
118 printf("\t\t \t\t 0x%08X \n",
119 cmd->response[3]);
120 printf("\n");
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
123 int j;
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
126 ptr += 3;
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
129 printf("\n");
130 }
131 break;
132 case MMC_RSP_R3:
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
134 cmd->response[0]);
135 break;
136 default:
137 printf("\t\tERROR MMC rsp not supported\n");
138 break;
139 }
140 }
141}
142
143void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
144{
145 int status;
146
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
149}
150#endif
151
152#if !CONFIG_IS_ENABLED(DM_MMC)
153int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
154{
155 int ret;
156
157 mmmc_trace_before_send(mmc, cmd);
158 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
159 mmmc_trace_after_send(mmc, cmd, ret);
160
161 return ret;
162}
163#endif
164
165int mmc_send_status(struct mmc *mmc, int timeout)
166{
167 struct mmc_cmd cmd;
168 int err, retries = 5;
169
170 cmd.cmdidx = MMC_CMD_SEND_STATUS;
171 cmd.resp_type = MMC_RSP_R1;
172 if (!mmc_host_is_spi(mmc))
173 cmd.cmdarg = mmc->rca << 16;
174
175 while (1) {
176 err = mmc_send_cmd(mmc, &cmd, NULL);
177 if (!err) {
178 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
179 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
180 MMC_STATE_PRG)
181 break;
182 else if (cmd.response[0] & MMC_STATUS_MASK) {
183#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
184 printf("Status Error: 0x%08X\n",
185 cmd.response[0]);
186#endif
187 return -ECOMM;
188 }
189 } else if (--retries < 0)
190 return err;
191
192 if (timeout-- <= 0)
193 break;
194
195 udelay(1000);
196 }
197
198 mmc_trace_state(mmc, &cmd);
199 if (timeout <= 0) {
200#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
201 printf("Timeout waiting card ready\n");
202#endif
203 return -ETIMEDOUT;
204 }
205
206 return 0;
207}
208
209int mmc_set_blocklen(struct mmc *mmc, int len)
210{
211 struct mmc_cmd cmd;
212
213 if (mmc->ddr_mode)
214 return 0;
215
216 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
217 cmd.resp_type = MMC_RSP_R1;
218 cmd.cmdarg = len;
219
220 return mmc_send_cmd(mmc, &cmd, NULL);
221}
222
223static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
224 lbaint_t blkcnt)
225{
226 struct mmc_cmd cmd;
227 struct mmc_data data;
228
229 if (blkcnt > 1)
230 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
231 else
232 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
233
234 if (mmc->high_capacity)
235 cmd.cmdarg = start;
236 else
237 cmd.cmdarg = start * mmc->read_bl_len;
238
239 cmd.resp_type = MMC_RSP_R1;
240
241 data.dest = dst;
242 data.blocks = blkcnt;
243 data.blocksize = mmc->read_bl_len;
244 data.flags = MMC_DATA_READ;
245
246 if (mmc_send_cmd(mmc, &cmd, &data))
247 return 0;
248
249 if (blkcnt > 1) {
250 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
251 cmd.cmdarg = 0;
252 cmd.resp_type = MMC_RSP_R1b;
253 if (mmc_send_cmd(mmc, &cmd, NULL)) {
254#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
255 printf("mmc fail to send stop cmd\n");
256#endif
257 return 0;
258 }
259 }
260
261 return blkcnt;
262}
263
264#if CONFIG_IS_ENABLED(BLK)
265ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
266#else
267ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
268 void *dst)
269#endif
270{
271#if CONFIG_IS_ENABLED(BLK)
272 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
273#endif
274 int dev_num = block_dev->devnum;
275 int err;
276 lbaint_t cur, blocks_todo = blkcnt;
277
278 if (blkcnt == 0)
279 return 0;
280
281 struct mmc *mmc = find_mmc_device(dev_num);
282 if (!mmc)
283 return 0;
284
285 if (CONFIG_IS_ENABLED(MMC_TINY))
286 err = mmc_switch_part(mmc, block_dev->hwpart);
287 else
288 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
289
290 if (err < 0)
291 return 0;
292
293 if ((start + blkcnt) > block_dev->lba) {
294#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
295 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
296 start + blkcnt, block_dev->lba);
297#endif
298 return 0;
299 }
300
301 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
302 debug("%s: Failed to set blocklen\n", __func__);
303 return 0;
304 }
305
306 do {
307 cur = (blocks_todo > mmc->cfg->b_max) ?
308 mmc->cfg->b_max : blocks_todo;
309 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
310 debug("%s: Failed to read blocks\n", __func__);
311 return 0;
312 }
313 blocks_todo -= cur;
314 start += cur;
315 dst += cur * mmc->read_bl_len;
316 } while (blocks_todo > 0);
317
318 return blkcnt;
319}
320
321static int mmc_go_idle(struct mmc *mmc)
322{
323 struct mmc_cmd cmd;
324 int err;
325
326 udelay(1000);
327
328 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
329 cmd.cmdarg = 0;
330 cmd.resp_type = MMC_RSP_NONE;
331
332 err = mmc_send_cmd(mmc, &cmd, NULL);
333
334 if (err)
335 return err;
336
337 udelay(2000);
338
339 return 0;
340}
341
342#ifndef CONFIG_DM_MMC
343static int mmc_set_voltage(struct mmc *mmc)
344{
345 int err = 0;
346
347 if (mmc->cfg->ops->set_voltage) {
348 err = mmc->cfg->ops->set_voltage(mmc);
349 if (err)
350 return err;
351 }
352
353 return err;
354}
355#endif
356
357static int mmc_switch_voltage(struct mmc *mmc)
358{
359 struct mmc_cmd cmd;
360 int err = 0;
361
362 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
363 cmd.cmdarg = 0;
364 cmd.resp_type = MMC_RSP_NONE;
365
366 err = mmc_send_cmd(mmc, &cmd, NULL);
367 if (err)
368 return err;
369
370 err = mmc_set_voltage(mmc);
371
372 return err;
373}
374
375static int mmc_host_uhs(struct mmc *mmc)
376{
377 return mmc->cfg->host_caps &
378 (MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 |
379 MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 |
380 MMC_MODE_UHS_DDR50);
381}
382
383static int sd_send_op_cond(struct mmc *mmc)
384{
385 int timeout = 1000;
386 int err;
387 struct mmc_cmd cmd;
388
389 while (1) {
390 cmd.cmdidx = MMC_CMD_APP_CMD;
391 cmd.resp_type = MMC_RSP_R1;
392 cmd.cmdarg = 0;
393
394 err = mmc_send_cmd(mmc, &cmd, NULL);
395
396 if (err)
397 return err;
398
399 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
400 cmd.resp_type = MMC_RSP_R3;
401
402
403
404
405
406
407
408
409 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
410 (mmc->cfg->voltages & 0xff8000);
411
412 if (mmc->version == SD_VERSION_2)
413 cmd.cmdarg |= OCR_HCS;
414
415 if (mmc_host_uhs(mmc))
416 cmd.cmdarg |= SD_OCR_S18R;
417
418 err = mmc_send_cmd(mmc, &cmd, NULL);
419
420 if (err)
421 return err;
422
423 if (cmd.response[0] & OCR_BUSY)
424 break;
425
426 if (timeout-- <= 0)
427 return -EOPNOTSUPP;
428
429 udelay(1000);
430 }
431
432 if (mmc->version != SD_VERSION_2)
433 mmc->version = SD_VERSION_1_0;
434
435 if (mmc_host_is_spi(mmc)) {
436 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
437 cmd.resp_type = MMC_RSP_R3;
438 cmd.cmdarg = 0;
439
440 err = mmc_send_cmd(mmc, &cmd, NULL);
441
442 if (err)
443 return err;
444 }
445
446 mmc->ocr = cmd.response[0];
447
448 if (mmc->ocr & SD_OCR_S18R) {
449 err = mmc_switch_voltage(mmc);
450 if (err)
451 return err;
452 mmc->is_uhs = 1;
453 }
454
455 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
456 mmc->rca = 0;
457
458 return 0;
459}
460
461static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
462{
463 struct mmc_cmd cmd;
464 int err;
465
466 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
467 cmd.resp_type = MMC_RSP_R3;
468 cmd.cmdarg = 0;
469 if (use_arg && !mmc_host_is_spi(mmc))
470 cmd.cmdarg = OCR_HCS |
471 (mmc->cfg->voltages &
472 (mmc->ocr & OCR_VOLTAGE_MASK)) |
473 (mmc->ocr & OCR_ACCESS_MODE);
474
475 err = mmc_send_cmd(mmc, &cmd, NULL);
476 if (err)
477 return err;
478 mmc->ocr = cmd.response[0];
479 return 0;
480}
481
482static int mmc_send_op_cond(struct mmc *mmc)
483{
484 int err, i;
485
486
487 mmc_go_idle(mmc);
488
489
490 for (i = 0; i < 2; i++) {
491 err = mmc_send_op_cond_iter(mmc, i != 0);
492 if (err)
493 return err;
494
495
496 if (mmc->ocr & OCR_BUSY)
497 break;
498 }
499 mmc->op_cond_pending = 1;
500 return 0;
501}
502
503static int mmc_complete_op_cond(struct mmc *mmc)
504{
505 struct mmc_cmd cmd;
506 int timeout = 1000;
507 uint start;
508 int err;
509
510 mmc->op_cond_pending = 0;
511 if (!(mmc->ocr & OCR_BUSY)) {
512
513 mmc_go_idle(mmc);
514
515 start = get_timer(0);
516 while (1) {
517 err = mmc_send_op_cond_iter(mmc, 1);
518 if (err)
519 return err;
520 if (mmc->ocr & OCR_BUSY)
521 break;
522 if (get_timer(start) > timeout)
523 return -EOPNOTSUPP;
524 udelay(100);
525 }
526 }
527
528 if (mmc_host_is_spi(mmc)) {
529 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
530 cmd.resp_type = MMC_RSP_R3;
531 cmd.cmdarg = 0;
532
533 err = mmc_send_cmd(mmc, &cmd, NULL);
534
535 if (err)
536 return err;
537
538 mmc->ocr = cmd.response[0];
539 }
540
541 mmc->version = MMC_VERSION_UNKNOWN;
542
543 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
544 mmc->rca = 1;
545
546 return 0;
547}
548
549
550static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
551{
552 struct mmc_cmd cmd;
553 struct mmc_data data;
554 int err;
555
556
557 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
558 cmd.resp_type = MMC_RSP_R1;
559 cmd.cmdarg = 0;
560
561 data.dest = (char *)ext_csd;
562 data.blocks = 1;
563 data.blocksize = MMC_MAX_BLOCK_LEN;
564 data.flags = MMC_DATA_READ;
565
566 err = mmc_send_cmd(mmc, &cmd, &data);
567
568 return err;
569}
570
571int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
572{
573 struct mmc_cmd cmd;
574 int timeout = 1000;
575 int retries = 3;
576 int ret;
577
578 cmd.cmdidx = MMC_CMD_SWITCH;
579 cmd.resp_type = MMC_RSP_R1b;
580 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
581 (index << 16) |
582 (value << 8);
583
584 while (retries > 0) {
585 ret = mmc_send_cmd(mmc, &cmd, NULL);
586
587
588 if (!ret) {
589 ret = mmc_send_status(mmc, timeout);
590 return ret;
591 }
592
593 retries--;
594 }
595
596 return ret;
597
598}
599
600#ifndef CONFIG_DM_MMC
601static void mmc_set_ios(struct mmc *mmc)
602{
603 if (mmc->cfg->ops->set_ios)
604 mmc->cfg->ops->set_ios(mmc);
605}
606#endif
607
608static void mmc_set_bus_width(struct mmc *mmc, uint width)
609{
610 mmc->bus_width = width;
611
612 mmc_set_ios(mmc);
613}
614
615static int mmc_select_bus_width(struct mmc *mmc)
616{
617
618 int idx;
619 int err;
620 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
621 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
622
623
624
625 static unsigned ext_csd_bits[] = {
626 EXT_CSD_BUS_WIDTH_8,
627 EXT_CSD_BUS_WIDTH_4,
628 };
629
630
631 static unsigned ext_to_hostcaps[] = {
632 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
633 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
634 };
635
636
637 static unsigned widths[] = {
638 8, 4,
639 };
640
641 err = mmc_send_ext_csd(mmc, ext_csd);
642
643 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
644 unsigned int extw = ext_csd_bits[idx];
645 unsigned int caps = ext_to_hostcaps[extw];
646
647
648
649
650
651
652
653 if (extw == EXT_CSD_BUS_WIDTH_1 &&
654 mmc->bus_width == 1) {
655 err = 0;
656 break;
657 }
658
659
660
661
662
663 if ((mmc->card_caps & caps) != caps)
664 continue;
665
666 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
667 EXT_CSD_BUS_WIDTH, extw);
668
669 if (err)
670 continue;
671
672 mmc_set_bus_width(mmc, widths[idx]);
673
674 err = mmc_send_ext_csd(mmc, test_csd);
675 if (err)
676 continue;
677
678
679 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
680 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
681 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
682 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
683 ext_csd[EXT_CSD_REV]
684 == test_csd[EXT_CSD_REV] &&
685 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
686 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
687 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
688 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
689 break;
690 else
691 err = -EBADMSG;
692 }
693
694 if (err)
695 return err;
696
697 return 0;
698}
699
700static int mmc_change_freq(struct mmc *mmc)
701{
702 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
703 char cardtype;
704 int err;
705
706 mmc->card_caps = 0;
707
708 if (mmc_host_is_spi(mmc))
709 return 0;
710
711
712 if (mmc->version < MMC_VERSION_4)
713 return 0;
714
715 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
716
717 err = mmc_send_ext_csd(mmc, ext_csd);
718
719 if (err)
720 return err;
721
722 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
723
724 if (mmc->forcehs)
725 cardtype &= ~EXT_CSD_CARD_TYPE_HS200;
726
727 if (cardtype & EXT_CSD_CARD_TYPE_HS200) {
728 err = mmc_select_bus_width(mmc);
729 if (err)
730 return err;
731 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
732 EXT_CSD_HS_TIMING,
733 EXT_CSD_HS_TIMING_HS200);
734 } else {
735 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
736 EXT_CSD_HS_TIMING,
737 EXT_CSD_HS_TIMING_HIGH_SPEED);
738 }
739 if (err)
740 return err;
741
742
743 err = mmc_send_ext_csd(mmc, ext_csd);
744
745 if (err)
746 return err;
747
748
749 if (!ext_csd[EXT_CSD_HS_TIMING])
750 return 0;
751
752
753 if (cardtype & EXT_CSD_CARD_TYPE_HS200) {
754 mmc->card_caps |= MMC_MODE_HS200;
755 } else if (cardtype & EXT_CSD_CARD_TYPE_52) {
756 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
757 mmc->card_caps |= MMC_MODE_DDR_52MHz;
758 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
759 } else {
760 mmc->card_caps |= MMC_MODE_HS;
761 }
762
763 return 0;
764}
765
766static int mmc_set_capacity(struct mmc *mmc, int part_num)
767{
768 switch (part_num) {
769 case 0:
770 mmc->capacity = mmc->capacity_user;
771 break;
772 case 1:
773 case 2:
774 mmc->capacity = mmc->capacity_boot;
775 break;
776 case 3:
777 mmc->capacity = mmc->capacity_rpmb;
778 break;
779 case 4:
780 case 5:
781 case 6:
782 case 7:
783 mmc->capacity = mmc->capacity_gp[part_num - 4];
784 break;
785 default:
786 return -1;
787 }
788
789 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
790
791 return 0;
792}
793
794static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
795{
796 int ret;
797
798 if (((part_num & PART_ACCESS_MASK) == PART_ACCESS_BOOT0) &&
799 (mmc->card_caps == MMC_MODE_HS200)) {
800 mmc->forcehs = 1;
801 ret = mmc_change_freq(mmc);
802 if (ret)
803 return ret;
804
805 mmc->card_caps &= mmc->cfg->host_caps;
806 if (mmc->card_caps & MMC_MODE_HS) {
807 if (mmc->card_caps & MMC_MODE_HS_52MHz)
808 mmc->tran_speed = 52000000;
809 else
810 mmc->tran_speed = 26000000;
811 }
812 mmc_set_clock(mmc, mmc->tran_speed);
813 }
814
815 if (((part_num & PART_ACCESS_MASK) != PART_ACCESS_BOOT0) &&
816 mmc->forcehs) {
817 mmc->forcehs = 0;
818 ret = mmc_change_freq(mmc);
819 if (ret)
820 return ret;
821
822 mmc->card_caps &= mmc->cfg->host_caps;
823 if (mmc->card_caps & MMC_MODE_HS200) {
824 mmc->tran_speed = 200000000;
825 } else if (mmc->card_caps & MMC_MODE_HS) {
826 if (mmc->card_caps & MMC_MODE_HS_52MHz)
827 mmc->tran_speed = 52000000;
828 else
829 mmc->tran_speed = 26000000;
830 }
831
832 mmc_set_clock(mmc, mmc->tran_speed);
833
834 if ((mmc->card_caps & MMC_MODE_HS200) &&
835 (mmc->cfg->host_caps & MMC_MODE_NEEDS_TUNING)) {
836 ret = mmc_execute_tuning(mmc);
837 if (ret)
838 return ret;
839 }
840 }
841
842 return 0;
843}
844
845int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
846{
847 int ret;
848
849 ret = mmc_boot_part_access_chk(mmc, part_num);
850 if (ret)
851 return ret;
852
853 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
854 (mmc->part_config & ~PART_ACCESS_MASK)
855 | (part_num & PART_ACCESS_MASK));
856
857
858
859
860
861 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
862 ret = mmc_set_capacity(mmc, part_num);
863 mmc_get_blk_desc(mmc)->hwpart = part_num;
864 }
865
866 return ret;
867}
868
869int mmc_hwpart_config(struct mmc *mmc,
870 const struct mmc_hwpart_conf *conf,
871 enum mmc_hwpart_conf_mode mode)
872{
873 u8 part_attrs = 0;
874 u32 enh_size_mult;
875 u32 enh_start_addr;
876 u32 gp_size_mult[4];
877 u32 max_enh_size_mult;
878 u32 tot_enh_size_mult = 0;
879 u8 wr_rel_set;
880 int i, pidx, err;
881 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
882
883 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
884 return -EINVAL;
885
886 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
887 printf("eMMC >= 4.4 required for enhanced user data area\n");
888 return -EMEDIUMTYPE;
889 }
890
891 if (!(mmc->part_support & PART_SUPPORT)) {
892 printf("Card does not support partitioning\n");
893 return -EMEDIUMTYPE;
894 }
895
896 if (!mmc->hc_wp_grp_size) {
897 printf("Card does not define HC WP group size\n");
898 return -EMEDIUMTYPE;
899 }
900
901
902 if (conf->user.enh_size) {
903 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
904 conf->user.enh_start % mmc->hc_wp_grp_size) {
905 printf("User data enhanced area not HC WP group "
906 "size aligned\n");
907 return -EINVAL;
908 }
909 part_attrs |= EXT_CSD_ENH_USR;
910 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
911 if (mmc->high_capacity) {
912 enh_start_addr = conf->user.enh_start;
913 } else {
914 enh_start_addr = (conf->user.enh_start << 9);
915 }
916 } else {
917 enh_size_mult = 0;
918 enh_start_addr = 0;
919 }
920 tot_enh_size_mult += enh_size_mult;
921
922 for (pidx = 0; pidx < 4; pidx++) {
923 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
924 printf("GP%i partition not HC WP group size "
925 "aligned\n", pidx+1);
926 return -EINVAL;
927 }
928 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
929 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
930 part_attrs |= EXT_CSD_ENH_GP(pidx);
931 tot_enh_size_mult += gp_size_mult[pidx];
932 }
933 }
934
935 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
936 printf("Card does not support enhanced attribute\n");
937 return -EMEDIUMTYPE;
938 }
939
940 err = mmc_send_ext_csd(mmc, ext_csd);
941 if (err)
942 return err;
943
944 max_enh_size_mult =
945 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
946 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
947 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
948 if (tot_enh_size_mult > max_enh_size_mult) {
949 printf("Total enhanced size exceeds maximum (%u > %u)\n",
950 tot_enh_size_mult, max_enh_size_mult);
951 return -EMEDIUMTYPE;
952 }
953
954
955
956
957
958 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
959 if (conf->user.wr_rel_change) {
960 if (conf->user.wr_rel_set)
961 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
962 else
963 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
964 }
965 for (pidx = 0; pidx < 4; pidx++) {
966 if (conf->gp_part[pidx].wr_rel_change) {
967 if (conf->gp_part[pidx].wr_rel_set)
968 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
969 else
970 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
971 }
972 }
973
974 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
975 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
976 puts("Card does not support host controlled partition write "
977 "reliability settings\n");
978 return -EMEDIUMTYPE;
979 }
980
981 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
982 EXT_CSD_PARTITION_SETTING_COMPLETED) {
983 printf("Card already partitioned\n");
984 return -EPERM;
985 }
986
987 if (mode == MMC_HWPART_CONF_CHECK)
988 return 0;
989
990
991 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
992 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
993 EXT_CSD_ERASE_GROUP_DEF, 1);
994
995 if (err)
996 return err;
997
998 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
999
1000
1001 mmc->erase_grp_size =
1002 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1003
1004 }
1005
1006
1007 for (i = 0; i < 4; i++) {
1008 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1009 EXT_CSD_ENH_START_ADDR+i,
1010 (enh_start_addr >> (i*8)) & 0xFF);
1011 if (err)
1012 return err;
1013 }
1014 for (i = 0; i < 3; i++) {
1015 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1016 EXT_CSD_ENH_SIZE_MULT+i,
1017 (enh_size_mult >> (i*8)) & 0xFF);
1018 if (err)
1019 return err;
1020 }
1021 for (pidx = 0; pidx < 4; pidx++) {
1022 for (i = 0; i < 3; i++) {
1023 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1024 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1025 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1026 if (err)
1027 return err;
1028 }
1029 }
1030 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1031 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1032 if (err)
1033 return err;
1034
1035 if (mode == MMC_HWPART_CONF_SET)
1036 return 0;
1037
1038
1039
1040
1041
1042 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1043 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1044 EXT_CSD_WR_REL_SET, wr_rel_set);
1045 if (err)
1046 return err;
1047 }
1048
1049
1050
1051
1052
1053
1054 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1055 EXT_CSD_PARTITION_SETTING,
1056 EXT_CSD_PARTITION_SETTING_COMPLETED);
1057 if (err)
1058 return err;
1059
1060 return 0;
1061}
1062
1063#if !CONFIG_IS_ENABLED(DM_MMC)
1064int mmc_getcd(struct mmc *mmc)
1065{
1066 int cd;
1067
1068 cd = board_mmc_getcd(mmc);
1069
1070 if (cd < 0) {
1071 if (mmc->cfg->ops->getcd)
1072 cd = mmc->cfg->ops->getcd(mmc);
1073 else
1074 cd = 1;
1075 }
1076
1077 return cd;
1078}
1079#endif
1080
1081static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1082{
1083 struct mmc_cmd cmd;
1084 struct mmc_data data;
1085
1086
1087 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1088 cmd.resp_type = MMC_RSP_R1;
1089 cmd.cmdarg = (mode << 31) | 0xffffff;
1090 cmd.cmdarg &= ~(0xf << (group * 4));
1091 cmd.cmdarg |= value << (group * 4);
1092
1093 data.dest = (char *)resp;
1094 data.blocksize = 64;
1095 data.blocks = 1;
1096 data.flags = MMC_DATA_READ;
1097
1098 return mmc_send_cmd(mmc, &cmd, &data);
1099}
1100
1101
1102static int sd_change_freq(struct mmc *mmc)
1103{
1104 int err;
1105 struct mmc_cmd cmd;
1106 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
1107 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1108 struct mmc_data data;
1109 int timeout;
1110 u8 mode;
1111
1112 mmc->card_caps = 0;
1113
1114 if (mmc_host_is_spi(mmc))
1115 return 0;
1116
1117
1118 cmd.cmdidx = MMC_CMD_APP_CMD;
1119 cmd.resp_type = MMC_RSP_R1;
1120 cmd.cmdarg = mmc->rca << 16;
1121
1122 err = mmc_send_cmd(mmc, &cmd, NULL);
1123
1124 if (err)
1125 return err;
1126
1127 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1128 cmd.resp_type = MMC_RSP_R1;
1129 cmd.cmdarg = 0;
1130
1131 timeout = 3;
1132
1133retry_scr:
1134 data.dest = (char *)scr;
1135 data.blocksize = 8;
1136 data.blocks = 1;
1137 data.flags = MMC_DATA_READ;
1138
1139 err = mmc_send_cmd(mmc, &cmd, &data);
1140
1141 if (err) {
1142 if (timeout--)
1143 goto retry_scr;
1144
1145 return err;
1146 }
1147
1148 mmc->scr[0] = __be32_to_cpu(scr[0]);
1149 mmc->scr[1] = __be32_to_cpu(scr[1]);
1150
1151 switch ((mmc->scr[0] >> 24) & 0xf) {
1152 case 0:
1153 mmc->version = SD_VERSION_1_0;
1154 break;
1155 case 1:
1156 mmc->version = SD_VERSION_1_10;
1157 break;
1158 case 2:
1159 mmc->version = SD_VERSION_2;
1160 if ((mmc->scr[0] >> 15) & 0x1)
1161 mmc->version = SD_VERSION_3;
1162 break;
1163 default:
1164 mmc->version = SD_VERSION_1_0;
1165 break;
1166 }
1167
1168 if (mmc->scr[0] & SD_DATA_4BIT)
1169 mmc->card_caps |= MMC_MODE_4BIT;
1170
1171
1172 if (mmc->version == SD_VERSION_1_0)
1173 return 0;
1174
1175 timeout = 4;
1176 while (timeout--) {
1177 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1178 (u8 *)switch_status);
1179
1180 if (err)
1181 return err;
1182
1183
1184 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1185 break;
1186 }
1187
1188 mode = MMC_TIMING_HS;
1189
1190 if ((mmc->version >= SD_VERSION_3) &&
1191 mmc_host_uhs(mmc)) {
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201 if (__be32_to_cpu(switch_status[3]) &
1202 (SD_UHS_SPEED_SDR104 | SD_UHS_SPEED_DDR50 |
1203 SD_UHS_SPEED_SDR50)) {
1204 mmc->is_uhs = 1;
1205 mmc_set_voltage(mmc);
1206 }
1207
1208 if (__be32_to_cpu(switch_status[3]) &
1209 SD_UHS_SPEED_SDR104) {
1210 mode = MMC_TIMING_UHS_SDR104;
1211 mmc->card_caps |= MMC_MODE_UHS_SDR104;
1212 mmc->tran_speed = 208000000;
1213 } else if (__be32_to_cpu(switch_status[3]) &
1214 SD_UHS_SPEED_SDR50) {
1215 mode = MMC_TIMING_UHS_SDR50;
1216 mmc->card_caps |= MMC_MODE_UHS_SDR50;
1217 mmc->tran_speed = 100000000;
1218 } else if (__be32_to_cpu(switch_status[3]) &
1219 SD_UHS_SPEED_DDR50) {
1220 mode = MMC_TIMING_UHS_DDR50;
1221 mmc->card_caps |= MMC_MODE_UHS_DDR50;
1222 mmc->tran_speed = 50000000;
1223 } else if (__be32_to_cpu(switch_status[3]) &
1224 SD_UHS_SPEED_SDR25) {
1225 mode = MMC_TIMING_UHS_SDR25;
1226 mmc->card_caps |= MMC_MODE_UHS_SDR25;
1227 mmc->tran_speed = 50000000;
1228 } else {
1229 mode = MMC_TIMING_UHS_SDR12;
1230 mmc->card_caps |= MMC_MODE_UHS_SDR12;
1231 mmc->tran_speed = 25000000;
1232 }
1233 mmc->uhsmode = mode;
1234 }
1235
1236
1237 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
1238 return 0;
1239
1240
1241
1242
1243
1244
1245
1246 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
1247 (mmc->cfg->host_caps & MMC_MODE_HS)))
1248 return 0;
1249
1250 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, mode, (u8 *)switch_status);
1251
1252 if (err)
1253 return err;
1254
1255 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
1256 mmc->card_caps |= MMC_MODE_HS;
1257
1258 return 0;
1259}
1260
1261static int sd_read_ssr(struct mmc *mmc)
1262{
1263 int err, i;
1264 struct mmc_cmd cmd;
1265 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1266 struct mmc_data data;
1267 int timeout = 3;
1268 unsigned int au, eo, et, es;
1269
1270 cmd.cmdidx = MMC_CMD_APP_CMD;
1271 cmd.resp_type = MMC_RSP_R1;
1272 cmd.cmdarg = mmc->rca << 16;
1273
1274 err = mmc_send_cmd(mmc, &cmd, NULL);
1275 if (err)
1276 return err;
1277
1278 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1279 cmd.resp_type = MMC_RSP_R1;
1280 cmd.cmdarg = 0;
1281
1282retry_ssr:
1283 data.dest = (char *)ssr;
1284 data.blocksize = 64;
1285 data.blocks = 1;
1286 data.flags = MMC_DATA_READ;
1287
1288 err = mmc_send_cmd(mmc, &cmd, &data);
1289 if (err) {
1290 if (timeout--)
1291 goto retry_ssr;
1292
1293 return err;
1294 }
1295
1296 for (i = 0; i < 16; i++)
1297 ssr[i] = be32_to_cpu(ssr[i]);
1298
1299 au = (ssr[2] >> 12) & 0xF;
1300 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1301 mmc->ssr.au = sd_au_size[au];
1302 es = (ssr[3] >> 24) & 0xFF;
1303 es |= (ssr[2] & 0xFF) << 8;
1304 et = (ssr[3] >> 18) & 0x3F;
1305 if (es && et) {
1306 eo = (ssr[3] >> 16) & 0x3;
1307 mmc->ssr.erase_timeout = (et * 1000) / es;
1308 mmc->ssr.erase_offset = eo * 1000;
1309 }
1310 } else {
1311 debug("Invalid Allocation Unit Size.\n");
1312 }
1313
1314 return 0;
1315}
1316
1317
1318
1319static const int fbase[] = {
1320 10000,
1321 100000,
1322 1000000,
1323 10000000,
1324};
1325
1326
1327
1328
1329static const u8 multipliers[] = {
1330 0,
1331 10,
1332 12,
1333 13,
1334 15,
1335 20,
1336 25,
1337 30,
1338 35,
1339 40,
1340 45,
1341 50,
1342 55,
1343 60,
1344 70,
1345 80,
1346};
1347
1348#if !CONFIG_IS_ENABLED(DM_MMC)
1349static void mmc_set_ios(struct mmc *mmc)
1350{
1351 if (mmc->cfg->ops->set_ios)
1352 mmc->cfg->ops->set_ios(mmc);
1353}
1354#endif
1355
1356void mmc_set_clock(struct mmc *mmc, uint clock)
1357{
1358 if (clock > mmc->cfg->f_max)
1359 clock = mmc->cfg->f_max;
1360
1361 if (clock < mmc->cfg->f_min)
1362 clock = mmc->cfg->f_min;
1363
1364 mmc->clock = clock;
1365
1366 mmc_set_ios(mmc);
1367}
1368
1369#ifndef CONFIG_DM_MMC
1370static int mmc_switch_uhs(struct mmc *mmc)
1371{
1372 int err = 0;
1373
1374 if (mmc->cfg->ops->set_uhs)
1375 err = mmc->cfg->ops->set_uhs(mmc);
1376
1377 return err;
1378}
1379
1380static int mmc_execute_tuning(struct mmc *mmc)
1381{
1382 int err = 0;
1383 u8 cmd;
1384
1385 if (mmc->cfg->ops->execute_tuning) {
1386 if (IS_SD(mmc))
1387 cmd = MMC_CMD_SEND_TUNING_BLOCK;
1388 else
1389 cmd = MMC_CMD_SEND_TUNING_BLOCK_HS200;
1390 err = mmc->cfg->ops->execute_tuning(mmc, cmd);
1391 }
1392
1393 return err;
1394}
1395#endif
1396
1397static int mmc_startup(struct mmc *mmc)
1398{
1399 int err, i;
1400 uint mult, freq;
1401 u64 cmult, csize, capacity;
1402 struct mmc_cmd cmd;
1403 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1404 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1405 bool has_parts = false;
1406 bool part_completed;
1407 struct blk_desc *bdesc;
1408
1409#ifdef CONFIG_MMC_SPI_CRC_ON
1410 if (mmc_host_is_spi(mmc)) {
1411 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1412 cmd.resp_type = MMC_RSP_R1;
1413 cmd.cmdarg = 1;
1414 err = mmc_send_cmd(mmc, &cmd, NULL);
1415
1416 if (err)
1417 return err;
1418 }
1419#endif
1420
1421
1422 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1423 MMC_CMD_ALL_SEND_CID;
1424 cmd.resp_type = MMC_RSP_R2;
1425 cmd.cmdarg = 0;
1426
1427 err = mmc_send_cmd(mmc, &cmd, NULL);
1428
1429 if (err)
1430 return err;
1431
1432 memcpy(mmc->cid, cmd.response, 16);
1433
1434
1435
1436
1437
1438
1439 if (!mmc_host_is_spi(mmc)) {
1440 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1441 cmd.cmdarg = mmc->rca << 16;
1442 cmd.resp_type = MMC_RSP_R6;
1443
1444 err = mmc_send_cmd(mmc, &cmd, NULL);
1445
1446 if (err)
1447 return err;
1448
1449 if (IS_SD(mmc))
1450 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1451 }
1452
1453
1454 cmd.cmdidx = MMC_CMD_SEND_CSD;
1455 cmd.resp_type = MMC_RSP_R2;
1456 cmd.cmdarg = mmc->rca << 16;
1457
1458 err = mmc_send_cmd(mmc, &cmd, NULL);
1459
1460 if (err)
1461 return err;
1462
1463 mmc->csd[0] = cmd.response[0];
1464 mmc->csd[1] = cmd.response[1];
1465 mmc->csd[2] = cmd.response[2];
1466 mmc->csd[3] = cmd.response[3];
1467
1468 if (mmc->version == MMC_VERSION_UNKNOWN) {
1469 int version = (cmd.response[0] >> 26) & 0xf;
1470
1471 switch (version) {
1472 case 0:
1473 mmc->version = MMC_VERSION_1_2;
1474 break;
1475 case 1:
1476 mmc->version = MMC_VERSION_1_4;
1477 break;
1478 case 2:
1479 mmc->version = MMC_VERSION_2_2;
1480 break;
1481 case 3:
1482 mmc->version = MMC_VERSION_3;
1483 break;
1484 case 4:
1485 mmc->version = MMC_VERSION_4;
1486 break;
1487 default:
1488 mmc->version = MMC_VERSION_1_2;
1489 break;
1490 }
1491 }
1492
1493
1494 freq = fbase[(cmd.response[0] & 0x7)];
1495 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1496
1497 mmc->tran_speed = freq * mult;
1498
1499 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1500 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1501
1502 if (IS_SD(mmc))
1503 mmc->write_bl_len = mmc->read_bl_len;
1504 else
1505 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1506
1507 if (mmc->high_capacity) {
1508 csize = (mmc->csd[1] & 0x3f) << 16
1509 | (mmc->csd[2] & 0xffff0000) >> 16;
1510 cmult = 8;
1511 } else {
1512 csize = (mmc->csd[1] & 0x3ff) << 2
1513 | (mmc->csd[2] & 0xc0000000) >> 30;
1514 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1515 }
1516
1517 mmc->capacity_user = (csize + 1) << (cmult + 2);
1518 mmc->capacity_user *= mmc->read_bl_len;
1519 mmc->capacity_boot = 0;
1520 mmc->capacity_rpmb = 0;
1521 for (i = 0; i < 4; i++)
1522 mmc->capacity_gp[i] = 0;
1523
1524 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1525 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1526
1527 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1528 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1529
1530 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1531 cmd.cmdidx = MMC_CMD_SET_DSR;
1532 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1533 cmd.resp_type = MMC_RSP_NONE;
1534 if (mmc_send_cmd(mmc, &cmd, NULL))
1535 printf("MMC: SET_DSR failed\n");
1536 }
1537
1538
1539 if (!mmc_host_is_spi(mmc)) {
1540 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1541 cmd.resp_type = MMC_RSP_R1;
1542 cmd.cmdarg = mmc->rca << 16;
1543 err = mmc_send_cmd(mmc, &cmd, NULL);
1544
1545 if (err)
1546 return err;
1547 }
1548
1549
1550
1551
1552 mmc->erase_grp_size = 1;
1553 mmc->part_config = MMCPART_NOAVAILABLE;
1554 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1555
1556 err = mmc_send_ext_csd(mmc, ext_csd);
1557 if (err)
1558 return err;
1559 if (ext_csd[EXT_CSD_REV] >= 2) {
1560
1561
1562
1563
1564
1565 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1566 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1567 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1568 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1569 capacity *= MMC_MAX_BLOCK_LEN;
1570 if ((capacity >> 20) > 2 * 1024)
1571 mmc->capacity_user = capacity;
1572 }
1573
1574 switch (ext_csd[EXT_CSD_REV]) {
1575 case 1:
1576 mmc->version = MMC_VERSION_4_1;
1577 break;
1578 case 2:
1579 mmc->version = MMC_VERSION_4_2;
1580 break;
1581 case 3:
1582 mmc->version = MMC_VERSION_4_3;
1583 break;
1584 case 5:
1585 mmc->version = MMC_VERSION_4_41;
1586 break;
1587 case 6:
1588 mmc->version = MMC_VERSION_4_5;
1589 break;
1590 case 7:
1591 mmc->version = MMC_VERSION_5_0;
1592 break;
1593 case 8:
1594 mmc->version = MMC_VERSION_5_1;
1595 break;
1596 }
1597
1598
1599
1600
1601
1602
1603 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1604 EXT_CSD_PARTITION_SETTING_COMPLETED);
1605
1606
1607 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1608 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1609 ext_csd[EXT_CSD_BOOT_MULT])
1610 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1611 if (part_completed &&
1612 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1613 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1614
1615 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1616
1617 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1618
1619 for (i = 0; i < 4; i++) {
1620 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1621 uint mult = (ext_csd[idx + 2] << 16) +
1622 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1623 if (mult)
1624 has_parts = true;
1625 if (!part_completed)
1626 continue;
1627 mmc->capacity_gp[i] = mult;
1628 mmc->capacity_gp[i] *=
1629 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1630 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1631 mmc->capacity_gp[i] <<= 19;
1632 }
1633
1634 if (part_completed) {
1635 mmc->enh_user_size =
1636 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1637 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1638 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1639 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1640 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1641 mmc->enh_user_size <<= 19;
1642 mmc->enh_user_start =
1643 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1644 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1645 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1646 ext_csd[EXT_CSD_ENH_START_ADDR];
1647 if (mmc->high_capacity)
1648 mmc->enh_user_start <<= 9;
1649 }
1650
1651
1652
1653
1654
1655
1656 if (part_completed)
1657 has_parts = true;
1658 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1659 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1660 has_parts = true;
1661 if (has_parts) {
1662 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1663 EXT_CSD_ERASE_GROUP_DEF, 1);
1664
1665 if (err)
1666 return err;
1667 else
1668 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1669 }
1670
1671 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1672
1673 mmc->erase_grp_size =
1674 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1675
1676
1677
1678
1679
1680 if (mmc->high_capacity && part_completed) {
1681 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1682 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1683 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1684 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1685 capacity *= MMC_MAX_BLOCK_LEN;
1686 mmc->capacity_user = capacity;
1687 }
1688 } else {
1689
1690 int erase_gsz, erase_gmul;
1691 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1692 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1693 mmc->erase_grp_size = (erase_gsz + 1)
1694 * (erase_gmul + 1);
1695 }
1696
1697 mmc->hc_wp_grp_size = 1024
1698 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1699 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1700
1701 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1702 }
1703
1704 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1705 if (err)
1706 return err;
1707
1708 if (IS_SD(mmc))
1709 err = sd_change_freq(mmc);
1710 else
1711 err = mmc_change_freq(mmc);
1712
1713 if (err)
1714 return err;
1715
1716
1717 mmc->card_caps &= mmc->cfg->host_caps;
1718
1719 if (IS_SD(mmc)) {
1720 if (mmc->card_caps & MMC_MODE_4BIT) {
1721 cmd.cmdidx = MMC_CMD_APP_CMD;
1722 cmd.resp_type = MMC_RSP_R1;
1723 cmd.cmdarg = mmc->rca << 16;
1724
1725 err = mmc_send_cmd(mmc, &cmd, NULL);
1726 if (err)
1727 return err;
1728
1729 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1730 cmd.resp_type = MMC_RSP_R1;
1731 cmd.cmdarg = 2;
1732 err = mmc_send_cmd(mmc, &cmd, NULL);
1733 if (err)
1734 return err;
1735
1736 mmc_set_bus_width(mmc, 4);
1737 }
1738
1739 err = sd_read_ssr(mmc);
1740 if (err)
1741 return err;
1742 if (mmc->card_caps & MMC_MODE_UHS) {
1743 err = mmc_switch_uhs(mmc);
1744 if (err)
1745 return err;
1746 } else {
1747 if (mmc->card_caps & MMC_MODE_HS)
1748 mmc->tran_speed = 50000000;
1749 else
1750 mmc->tran_speed = 25000000;
1751 }
1752 } else if ((mmc->version >= MMC_VERSION_4) &&
1753 ((ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_MASK) !=
1754 EXT_CSD_CARD_TYPE_HS200)) {
1755
1756 int idx;
1757
1758
1759 static unsigned ext_csd_bits[] = {
1760 EXT_CSD_DDR_BUS_WIDTH_8,
1761 EXT_CSD_DDR_BUS_WIDTH_4,
1762 EXT_CSD_BUS_WIDTH_8,
1763 EXT_CSD_BUS_WIDTH_4,
1764 EXT_CSD_BUS_WIDTH_1,
1765 };
1766
1767
1768 static unsigned ext_to_hostcaps[] = {
1769 [EXT_CSD_DDR_BUS_WIDTH_4] =
1770 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1771 [EXT_CSD_DDR_BUS_WIDTH_8] =
1772 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1773 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1774 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1775 };
1776
1777
1778 static unsigned widths[] = {
1779 8, 4, 8, 4, 1,
1780 };
1781
1782 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1783 unsigned int extw = ext_csd_bits[idx];
1784 unsigned int caps = ext_to_hostcaps[extw];
1785
1786
1787
1788
1789
1790
1791
1792 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1793 mmc->bus_width == 1) {
1794 err = 0;
1795 break;
1796 }
1797
1798
1799
1800
1801
1802 if ((mmc->card_caps & caps) != caps)
1803 continue;
1804
1805 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1806 EXT_CSD_BUS_WIDTH, extw);
1807
1808 if (err)
1809 continue;
1810
1811 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1812 mmc_set_bus_width(mmc, widths[idx]);
1813
1814 err = mmc_send_ext_csd(mmc, test_csd);
1815
1816 if (err)
1817 continue;
1818
1819
1820 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1821 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1822 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1823 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1824 ext_csd[EXT_CSD_REV]
1825 == test_csd[EXT_CSD_REV] &&
1826 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1827 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1828 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1829 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1830 break;
1831 else
1832 err = -EBADMSG;
1833 }
1834
1835 if (err)
1836 return err;
1837 }
1838
1839 if (!IS_SD(mmc)) {
1840 if (mmc->card_caps & MMC_MODE_HS200) {
1841 mmc->tran_speed = 200000000;
1842 } else if (mmc->card_caps & MMC_MODE_HS) {
1843 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1844 mmc->tran_speed = 52000000;
1845 else
1846 mmc->tran_speed = 26000000;
1847 }
1848 }
1849
1850 mmc_set_clock(mmc, mmc->tran_speed);
1851
1852 if ((mmc->card_caps & (MMC_MODE_UHS_SDR50 |
1853 MMC_MODE_UHS_SDR104 |
1854 MMC_MODE_HS200)) &&
1855 (mmc->cfg->host_caps & MMC_MODE_NEEDS_TUNING)) {
1856 err = mmc_execute_tuning(mmc);
1857 if (err)
1858 return err;
1859 }
1860
1861
1862 if (mmc->ddr_mode) {
1863 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1864 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1865 }
1866
1867
1868 bdesc = mmc_get_blk_desc(mmc);
1869 bdesc->lun = 0;
1870 bdesc->hwpart = 0;
1871 bdesc->type = 0;
1872 bdesc->blksz = mmc->read_bl_len;
1873 bdesc->log2blksz = LOG2(bdesc->blksz);
1874 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1875#if !defined(CONFIG_SPL_BUILD) || \
1876 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1877 !defined(CONFIG_USE_TINY_PRINTF))
1878 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1879 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1880 (mmc->cid[3] >> 16) & 0xffff);
1881 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1882 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1883 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1884 (mmc->cid[2] >> 24) & 0xff);
1885 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1886 (mmc->cid[2] >> 16) & 0xf);
1887#else
1888 bdesc->vendor[0] = 0;
1889 bdesc->product[0] = 0;
1890 bdesc->revision[0] = 0;
1891#endif
1892#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1893 part_init(bdesc);
1894#endif
1895
1896 return 0;
1897}
1898
1899static int mmc_send_if_cond(struct mmc *mmc)
1900{
1901 struct mmc_cmd cmd;
1902 int err;
1903
1904 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1905
1906 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1907 cmd.resp_type = MMC_RSP_R7;
1908
1909 err = mmc_send_cmd(mmc, &cmd, NULL);
1910
1911 if (err)
1912 return err;
1913
1914 if ((cmd.response[0] & 0xff) != 0xaa)
1915 return -EOPNOTSUPP;
1916 else
1917 mmc->version = SD_VERSION_2;
1918
1919 return 0;
1920}
1921
1922#if !CONFIG_IS_ENABLED(DM_MMC)
1923
1924__weak void board_mmc_power_init(void)
1925{
1926}
1927#endif
1928
1929static int mmc_power_init(struct mmc *mmc)
1930{
1931#if CONFIG_IS_ENABLED(DM_MMC)
1932#if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD)
1933 struct udevice *vmmc_supply;
1934 int ret;
1935
1936 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1937 &vmmc_supply);
1938 if (ret) {
1939 debug("%s: No vmmc supply\n", mmc->dev->name);
1940 return 0;
1941 }
1942
1943 ret = regulator_set_enable(vmmc_supply, true);
1944 if (ret) {
1945 puts("Error enabling VMMC supply\n");
1946 return ret;
1947 }
1948#endif
1949#else
1950
1951
1952
1953
1954 board_mmc_power_init();
1955#endif
1956 return 0;
1957}
1958
1959int mmc_start_init(struct mmc *mmc)
1960{
1961 bool no_card;
1962 int err;
1963
1964
1965 no_card = mmc_getcd(mmc) == 0;
1966#if !CONFIG_IS_ENABLED(DM_MMC)
1967 no_card = no_card || (mmc->cfg->ops->init == NULL);
1968#endif
1969 if (no_card) {
1970 mmc->has_init = 0;
1971#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1972 printf("MMC: no card present\n");
1973#endif
1974 return -ENOMEDIUM;
1975 }
1976
1977 if (mmc->has_init)
1978 return 0;
1979
1980#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1981 mmc_adapter_card_type_ident();
1982#endif
1983 err = mmc_power_init(mmc);
1984 if (err)
1985 return err;
1986
1987#if CONFIG_IS_ENABLED(DM_MMC)
1988
1989#else
1990
1991 err = mmc->cfg->ops->init(mmc);
1992 if (err)
1993 return err;
1994#endif
1995 mmc->ddr_mode = 0;
1996 mmc_set_bus_width(mmc, 1);
1997 mmc_set_clock(mmc, 1);
1998
1999
2000 err = mmc_go_idle(mmc);
2001
2002 if (err)
2003 return err;
2004
2005
2006 mmc_get_blk_desc(mmc)->hwpart = 0;
2007
2008
2009 err = mmc_send_if_cond(mmc);
2010
2011
2012 err = sd_send_op_cond(mmc);
2013
2014
2015 if (err == -ETIMEDOUT) {
2016 err = mmc_send_op_cond(mmc);
2017
2018 if (err) {
2019#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2020 printf("Card did not respond to voltage select!\n");
2021#endif
2022 return -EOPNOTSUPP;
2023 }
2024 }
2025
2026 if (!err)
2027 mmc->init_in_progress = 1;
2028
2029 return err;
2030}
2031
2032static int mmc_complete_init(struct mmc *mmc)
2033{
2034 int err = 0;
2035
2036 mmc->init_in_progress = 0;
2037 if (mmc->op_cond_pending)
2038 err = mmc_complete_op_cond(mmc);
2039
2040 if (!err)
2041 err = mmc_startup(mmc);
2042 if (err)
2043 mmc->has_init = 0;
2044 else
2045 mmc->has_init = 1;
2046 return err;
2047}
2048
2049int mmc_init(struct mmc *mmc)
2050{
2051 int err = 0;
2052 __maybe_unused unsigned start;
2053#if CONFIG_IS_ENABLED(DM_MMC)
2054 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2055
2056 upriv->mmc = mmc;
2057#endif
2058 if (mmc->has_init)
2059 return 0;
2060
2061 start = get_timer(0);
2062
2063 if (!mmc->init_in_progress)
2064 err = mmc_start_init(mmc);
2065
2066 if (!err)
2067 err = mmc_complete_init(mmc);
2068 if (err)
2069 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2070
2071 return err;
2072}
2073
2074int mmc_set_dsr(struct mmc *mmc, u16 val)
2075{
2076 mmc->dsr = val;
2077 return 0;
2078}
2079
2080
2081__weak int cpu_mmc_init(bd_t *bis)
2082{
2083 return -1;
2084}
2085
2086
2087__weak int board_mmc_init(bd_t *bis)
2088{
2089 return -1;
2090}
2091
2092void mmc_set_preinit(struct mmc *mmc, int preinit)
2093{
2094 mmc->preinit = preinit;
2095}
2096
2097#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2098static int mmc_probe(bd_t *bis)
2099{
2100 return 0;
2101}
2102#elif CONFIG_IS_ENABLED(DM_MMC)
2103static int mmc_probe(bd_t *bis)
2104{
2105 int ret, i;
2106 struct uclass *uc;
2107 struct udevice *dev;
2108
2109 ret = uclass_get(UCLASS_MMC, &uc);
2110 if (ret)
2111 return ret;
2112
2113
2114
2115
2116
2117
2118 for (i = 0; ; i++) {
2119 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2120 if (ret == -ENODEV)
2121 break;
2122 }
2123 uclass_foreach_dev(dev, uc) {
2124 ret = device_probe(dev);
2125 if (ret)
2126 printf("%s - probe failed: %d\n", dev->name, ret);
2127 }
2128
2129 return 0;
2130}
2131#else
2132static int mmc_probe(bd_t *bis)
2133{
2134 if (board_mmc_init(bis) < 0)
2135 cpu_mmc_init(bis);
2136
2137 return 0;
2138}
2139#endif
2140
2141int mmc_initialize(bd_t *bis)
2142{
2143 static int initialized = 0;
2144 int ret;
2145 if (initialized)
2146 return 0;
2147 initialized = 1;
2148
2149#if !CONFIG_IS_ENABLED(BLK)
2150#if !CONFIG_IS_ENABLED(MMC_TINY)
2151 mmc_list_init();
2152#endif
2153#endif
2154 ret = mmc_probe(bis);
2155 if (ret)
2156 return ret;
2157
2158#ifndef CONFIG_SPL_BUILD
2159 print_mmc_devices(',');
2160#endif
2161
2162 mmc_do_preinit();
2163 return 0;
2164}
2165
2166#ifdef CONFIG_CMD_BKOPS_ENABLE
2167int mmc_set_bkops_enable(struct mmc *mmc)
2168{
2169 int err;
2170 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2171
2172 err = mmc_send_ext_csd(mmc, ext_csd);
2173 if (err) {
2174 puts("Could not get ext_csd register values\n");
2175 return err;
2176 }
2177
2178 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2179 puts("Background operations not supported on device\n");
2180 return -EMEDIUMTYPE;
2181 }
2182
2183 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2184 puts("Background operations already enabled\n");
2185 return 0;
2186 }
2187
2188 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2189 if (err) {
2190 puts("Failed to enable manual background operations\n");
2191 return err;
2192 }
2193
2194 puts("Enabled manual background operations\n");
2195
2196 return 0;
2197}
2198#endif
2199
