LXR uboot/drivers/video/atmel

   1/*
   2 * Driver for AT91/AT32 LCD Controller
   3 *
   4 * Copyright (C) 2007 Atmel Corporation
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <atmel_lcd.h>
  11#include <dm.h>
  12#include <fdtdec.h>
  13#include <video.h>
  14#include <asm/io.h>
  15#include <asm/arch/gpio.h>
  16#include <asm/arch/clk.h>
  17#include <lcd.h>
  18#include <bmp_layout.h>
  19#include <atmel_lcdc.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23#ifdef CONFIG_DM_VIDEO
  24enum {
  25        /* Maximum LCD size we support */
  26        LCD_MAX_WIDTH           = 1366,
  27        LCD_MAX_HEIGHT          = 768,
  28        LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  29};
  30#endif
  31
  32struct atmel_fb_priv {
  33        struct display_timing timing;
  34};
  35
  36/* configurable parameters */
  37#define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  38#define ATMEL_LCDC_DMA_BURST_LEN        8
  39#ifndef ATMEL_LCDC_GUARD_TIME
  40#define ATMEL_LCDC_GUARD_TIME           1
  41#endif
  42
  43#if defined(CONFIG_AT91SAM9263)
  44#define ATMEL_LCDC_FIFO_SIZE            2048
  45#else
  46#define ATMEL_LCDC_FIFO_SIZE            512
  47#endif
  48
  49#define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  50#define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  51
  52#ifndef CONFIG_DM_VIDEO
  53ushort *configuration_get_cmap(void)
  54{
  55        return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  56}
  57
  58#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  59void fb_put_word(uchar **fb, uchar **from)
  60{
  61        *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  62        *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  63        *from += 2;
  64}
  65#endif
  66
  67#ifdef CONFIG_LCD_LOGO
  68#include <bmp_logo.h>
  69void lcd_logo_set_cmap(void)
  70{
  71        int i;
  72        uint lut_entry;
  73        ushort colreg;
  74        uint *cmap = (uint *)configuration_get_cmap();
  75
  76        for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  77                colreg = bmp_logo_palette[i];
  78#ifdef CONFIG_ATMEL_LCD_BGR555
  79                lut_entry = ((colreg & 0x000F) << 11) |
  80                                ((colreg & 0x00F0) <<  2) |
  81                                ((colreg & 0x0F00) >>  7);
  82#else
  83                lut_entry = ((colreg & 0x000F) << 1) |
  84                                ((colreg & 0x00F0) << 3) |
  85                                ((colreg & 0x0F00) << 4);
  86#endif
  87                *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  88                cmap++;
  89        }
  90}
  91#endif
  92
  93void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  94{
  95#if defined(CONFIG_ATMEL_LCD_BGR555)
  96        lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  97                    (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  98#else
  99        lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
 100                    (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
 101#endif
 102}
 103
 104void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 105{
 106        int i;
 107
 108        for (i = 0; i < colors; ++i) {
 109                struct bmp_color_table_entry cte = bmp->color_table[i];
 110                lcd_setcolreg(i, cte.red, cte.green, cte.blue);
 111        }
 112}
 113#endif
 114
 115static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 116                          bool tft, bool cont_pol_low, ulong lcdbase)
 117{
 118        unsigned long value;
 119        void *reg = (void *)addr;
 120
 121        /* Turn off the LCD controller and the DMA controller */
 122        lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 123                    ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 124
 125        /* Wait for the LCDC core to become idle */
 126        while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 127                udelay(10);
 128
 129        lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 130
 131        /* Reset LCDC DMA */
 132        lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 133
 134        /* ...set frame size and burst length = 8 words (?) */
 135        value = (timing->hactive.typ * timing->vactive.typ *
 136                 (1 << bpix)) / 32;
 137        value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 138        lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 139
 140        /* Set pixel clock */
 141        value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
 142        if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 143                value++;
 144        value = (value / 2) - 1;
 145
 146        if (!value) {
 147                lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 148        } else
 149                lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 150                            value << ATMEL_LCDC_CLKVAL_OFFSET);
 151
 152        /* Initialize control register 2 */
 153        value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 154        if (tft)
 155                value |= ATMEL_LCDC_DISTYPE_TFT;
 156
 157        if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 158                value |= ATMEL_LCDC_INVLINE_INVERTED;
 159        if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 160                value |= ATMEL_LCDC_INVFRAME_INVERTED;
 161        value |= bpix << 5;
 162        lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 163
 164        /* Vertical timing */
 165        value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
 166        value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
 167        value |= timing->vfront_porch.typ;
 168        /* Magic! (Datasheet says "Bit 31 must be written to 1") */
 169        value |= 1U << 31;
 170        lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 171
 172        /* Horizontal timing */
 173        value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
 174        value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
 175        value |= (timing->hback_porch.typ - 1);
 176        lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 177
 178        /* Display size */
 179        value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 180        value |= timing->vactive.typ - 1;
 181        lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 182
 183        /* FIFO Threshold: Use formula from data sheet */
 184        value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 185        lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 186
 187        /* Toggle LCD_MODE every frame */
 188        lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 189
 190        /* Disable all interrupts */
 191        lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 192
 193        /* Set contrast */
 194        value = ATMEL_LCDC_PS_DIV8 |
 195                ATMEL_LCDC_ENA_PWMENABLE;
 196        if (!cont_pol_low)
 197                value |= ATMEL_LCDC_POL_POSITIVE;
 198        lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
 199        lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 200
 201        /* Set framebuffer DMA base address and pixel offset */
 202        lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 203
 204        lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 205        lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 206                    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 207}
 208
 209#ifndef CONFIG_DM_VIDEO
 210void lcd_ctrl_init(void *lcdbase)
 211{
 212        struct display_timing timing;
 213
 214        timing.flags = 0;
 215        if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
 216                timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
 217        if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
 218                timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
 219        timing.pixelclock.typ = panel_info.vl_clk;
 220
 221        timing.hactive.typ = panel_info.vl_col;
 222        timing.hfront_porch.typ = panel_info.vl_right_margin;
 223        timing.hback_porch.typ = panel_info.vl_left_margin;
 224        timing.hsync_len.typ = panel_info.vl_hsync_len;
 225
 226        timing.vactive.typ = panel_info.vl_row;
 227        timing.vfront_porch.typ = panel_info.vl_clk;
 228        timing.vback_porch.typ = panel_info.vl_clk;
 229        timing.vsync_len.typ = panel_info.vl_clk;
 230
 231        atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
 232                      panel_info.vl_tft, panel_info.vl_cont_pol_low,
 233                      (ulong)lcdbase);
 234}
 235
 236ulong calc_fbsize(void)
 237{
 238        return ((panel_info.vl_col * panel_info.vl_row *
 239                NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 240}
 241#endif
 242
 243#ifdef CONFIG_DM_VIDEO
 244static int atmel_fb_lcd_probe(struct udevice *dev)
 245{
 246        struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 247        struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 248        struct atmel_fb_priv *priv = dev_get_priv(dev);
 249        struct display_timing *timing = &priv->timing;
 250
 251        /*
 252         * For now some values are hard-coded. We could use the device tree
 253         * bindings in simple-framebuffer.txt to specify the format/bpp and
 254         * some Atmel-specific binding for tft and cont_pol_low.
 255         */
 256        atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
 257                      uc_plat->base);
 258        uc_priv->xsize = timing->hactive.typ;
 259        uc_priv->ysize = timing->vactive.typ;
 260        uc_priv->bpix = VIDEO_BPP16;
 261        video_set_flush_dcache(dev, true);
 262        debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
 263              uc_plat->size, uc_priv->xsize, uc_priv->ysize);
 264
 265        return 0;
 266}
 267
 268static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
 269{
 270        struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
 271        struct atmel_fb_priv *priv = dev_get_priv(dev);
 272        struct display_timing *timing = &priv->timing;
 273        const void *blob = gd->fdt_blob;
 274
 275        if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 276                                         plat->timing_index, timing)) {
 277                debug("%s: Failed to decode display timing\n", __func__);
 278                return -EINVAL;
 279        }
 280
 281        return 0;
 282}
 283
 284static int atmel_fb_lcd_bind(struct udevice *dev)
 285{
 286        struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 287
 288        uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 289                        (1 << VIDEO_BPP16) / 8;
 290        debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 291
 292        return 0;
 293}
 294
 295static const struct udevice_id atmel_fb_lcd_ids[] = {
 296        { .compatible = "atmel,at91sam9g45-lcdc" },
 297        { }
 298};
 299
 300U_BOOT_DRIVER(atmel_fb) = {
 301        .name   = "atmel_fb",
 302        .id     = UCLASS_VIDEO,
 303        .of_match = atmel_fb_lcd_ids,
 304        .bind   = atmel_fb_lcd_bind,
 305        .ofdata_to_platdata     = atmel_fb_ofdata_to_platdata,
 306        .probe  = atmel_fb_lcd_probe,
 307        .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
 308        .priv_auto_alloc_size   = sizeof(struct atmel_fb_priv),
 309};
 310#endif
 311