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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_SYS_TEXT_BASE 0xfff80000
14
15#define CONFIG_SYS_SRIO
16#define CONFIG_SRIO1
17
18#define CONFIG_PCI1 1
19#define CONFIG_PCIE1 1
20#define CONFIG_FSL_PCI_INIT 1
21#define CONFIG_PCI_INDIRECT_BRIDGE 1
22#define CONFIG_FSL_PCIE_RESET 1
23#define CONFIG_SYS_PCI_64BIT 1
24#define CONFIG_TSEC_ENET
25#define CONFIG_QE
26#define CONFIG_ENV_OVERWRITE
27
28#ifndef __ASSEMBLY__
29extern unsigned long get_clock_freq(void);
30#endif
31#define CONFIG_SYS_CLK_FREQ 66000000
32
33
34
35
36#define CONFIG_L2_CACHE
37#define CONFIG_BTB
38
39
40
41
42#define CONFIG_ENABLE_36BIT_PHYS 1
43
44#define CONFIG_SYS_MEMTEST_START 0x00200000
45#define CONFIG_SYS_MEMTEST_END 0x00400000
46
47#define CONFIG_SYS_CCSRBAR 0xe0000000
48#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
49
50
51#undef CONFIG_FSL_DDR_INTERACTIVE
52#define CONFIG_SPD_EEPROM
53#define CONFIG_DDR_SPD
54#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
55
56#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57
58#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
59#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
60
61#define CONFIG_DIMM_SLOTS_PER_CTLR 1
62#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
63
64
65#define SPD_EEPROM_ADDRESS 0x51
66
67
68#ifndef CONFIG_SPD_EEPROM
69#error ("CONFIG_SPD_EEPROM is required")
70#endif
71
72#undef CONFIG_CLOCKS_IN_MHZ
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106
107#define CONFIG_SYS_BCSR_BASE 0xf8000000
108
109#define CONFIG_SYS_FLASH_BASE 0xfe000000
110
111
112#define CONFIG_SYS_BR0_PRELIM 0xfe001001
113#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
114
115
116#define CONFIG_SYS_BR1_PRELIM 0xf8000801
117#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
118
119
120#define CONFIG_SYS_MAX_FLASH_BANKS 1
121#define CONFIG_SYS_MAX_FLASH_SECT 512
122#undef CONFIG_SYS_FLASH_CHECKSUM
123#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500
125
126#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
127
128#define CONFIG_FLASH_CFI_DRIVER
129#define CONFIG_SYS_FLASH_CFI
130#define CONFIG_SYS_FLASH_EMPTY_INFO
131
132
133
134
135#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
136#define CONFIG_SYS_LBC_SDRAM_SIZE 64
137
138
139#define CONFIG_SYS_BR2_PRELIM 0xf0001861
140#define CONFIG_SYS_OR2_PRELIM 0xfc006901
141
142#define CONFIG_SYS_LBC_LCRR 0x00030004
143#define CONFIG_SYS_LBC_LBCR 0x00000000
144#define CONFIG_SYS_LBC_LSRT 0x20000000
145#define CONFIG_SYS_LBC_MRTPR 0x00000000
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152
153#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
154 | LSDMR_PRETOACT7 \
155 | LSDMR_ACTTORW7 \
156 | LSDMR_BL8 \
157 | LSDMR_WRC4 \
158 | LSDMR_CL3 \
159 | LSDMR_RFEN \
160 )
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190
191#define CONFIG_SYS_BCSR (0xf8000000)
192
193
194#define CONFIG_SYS_BR4_PRELIM 0xf8008801
195#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
196
197
198#define CONFIG_SYS_BR5_PRELIM 0xf8010801
199#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
200
201#define CONFIG_SYS_INIT_RAM_LOCK 1
202#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
203#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
204
205#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207
208#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
209#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
210
211
212#define CONFIG_CONS_INDEX 1
213#define CONFIG_SYS_NS16550_SERIAL
214#define CONFIG_SYS_NS16550_REG_SIZE 1
215#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
216
217#define CONFIG_SYS_BAUDRATE_TABLE \
218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
219
220#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
221#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
222
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225
226#define CONFIG_SYS_I2C
227#define CONFIG_SYS_I2C_FSL
228#define CONFIG_SYS_FSL_I2C_SPEED 400000
229#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
231#define CONFIG_SYS_FSL_I2C2_SPEED 400000
232#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
233#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
234#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
235#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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240
241#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
242#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
243#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
244#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
245#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
246#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
247#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
248#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000
249
250#define CONFIG_SYS_PCIE1_NAME "Slot"
251#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
252#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
253#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
254#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
255#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
256#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
257#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
258#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
259
260#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
261#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
262#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
263#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
264
265#ifdef CONFIG_QE
266
267
268
269#define CONFIG_UEC_ETH
270#ifndef CONFIG_TSEC_ENET
271#define CONFIG_ETHPRIME "UEC0"
272#endif
273#define CONFIG_PHY_MODE_NEED_CHANGE
274#define CONFIG_eTSEC_MDIO_BUS
275
276#ifdef CONFIG_eTSEC_MDIO_BUS
277#define CONFIG_MIIM_ADDRESS 0xE0024520
278#endif
279
280#define CONFIG_UEC_ETH1
281
282#ifdef CONFIG_UEC_ETH1
283#define CONFIG_SYS_UEC1_UCC_NUM 0
284#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
285#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
286#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
287#define CONFIG_SYS_UEC1_PHY_ADDR 7
288#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
289#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
290#endif
291
292#define CONFIG_UEC_ETH2
293
294#ifdef CONFIG_UEC_ETH2
295#define CONFIG_SYS_UEC2_UCC_NUM 1
296#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
297#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
298#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
299#define CONFIG_SYS_UEC2_PHY_ADDR 1
300#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
301#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
302#endif
303#endif
304
305#if defined(CONFIG_PCI)
306#undef CONFIG_EEPRO100
307#undef CONFIG_TULIP
308
309#undef CONFIG_PCI_SCAN_SHOW
310#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
311
312#endif
313
314#if defined(CONFIG_TSEC_ENET)
315
316#define CONFIG_MII 1
317#define CONFIG_TSEC1 1
318#define CONFIG_TSEC1_NAME "eTSEC0"
319#define CONFIG_TSEC2 1
320#define CONFIG_TSEC2_NAME "eTSEC1"
321
322#define TSEC1_PHY_ADDR 2
323#define TSEC2_PHY_ADDR 3
324
325#define TSEC1_PHYIDX 0
326#define TSEC2_PHYIDX 0
327
328#define TSEC1_FLAGS TSEC_GIGABIT
329#define TSEC2_FLAGS TSEC_GIGABIT
330
331
332#define CONFIG_ETHPRIME "eTSEC0"
333
334#endif
335
336
337
338
339#define CONFIG_ENV_SECT_SIZE 0x20000
340#define CONFIG_ENV_SIZE 0x2000
341#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
342
343#define CONFIG_LOADS_ECHO 1
344#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
345
346
347
348
349#define CONFIG_BOOTP_BOOTFILESIZE
350#define CONFIG_BOOTP_BOOTPATH
351#define CONFIG_BOOTP_GATEWAY
352#define CONFIG_BOOTP_HOSTNAME
353
354#undef CONFIG_WATCHDOG
355
356
357
358
359#define CONFIG_SYS_LONGHELP
360#define CONFIG_CMDLINE_EDITING
361#define CONFIG_AUTO_COMPLETE
362#define CONFIG_SYS_LOAD_ADDR 0x2000000
363
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367
368
369#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
370#define CONFIG_SYS_BOOTM_LEN (64 << 20)
371
372#if defined(CONFIG_CMD_KGDB)
373#define CONFIG_KGDB_BAUDRATE 230400
374#endif
375
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380
381#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
382#define CONFIG_HAS_ETH0
383#define CONFIG_HAS_ETH1
384#define CONFIG_HAS_ETH2
385#define CONFIG_HAS_ETH3
386#endif
387
388#define CONFIG_IPADDR 192.168.1.253
389
390#define CONFIG_HOSTNAME unknown
391#define CONFIG_ROOTPATH "/nfsroot"
392#define CONFIG_BOOTFILE "your.uImage"
393
394#define CONFIG_SERVERIP 192.168.1.1
395#define CONFIG_GATEWAYIP 192.168.1.1
396#define CONFIG_NETMASK 255.255.255.0
397
398#define CONFIG_LOADADDR 200000
399
400#define CONFIG_EXTRA_ENV_SETTINGS \
401 "netdev=eth0\0" \
402 "consoledev=ttyS0\0" \
403 "ramdiskaddr=600000\0" \
404 "ramdiskfile=your.ramdisk.u-boot\0" \
405 "fdtaddr=400000\0" \
406 "fdtfile=your.fdt.dtb\0" \
407 "nfsargs=setenv bootargs root=/dev/nfs rw " \
408 "nfsroot=$serverip:$rootpath " \
409 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
410 "console=$consoledev,$baudrate $othbootargs\0" \
411 "ramargs=setenv bootargs root=/dev/ram rw " \
412 "console=$consoledev,$baudrate $othbootargs\0" \
413
414#define CONFIG_NFSBOOTCOMMAND \
415 "run nfsargs;" \
416 "tftp $loadaddr $bootfile;" \
417 "tftp $fdtaddr $fdtfile;" \
418 "bootm $loadaddr - $fdtaddr"
419
420#define CONFIG_RAMBOOTCOMMAND \
421 "run ramargs;" \
422 "tftp $ramdiskaddr $ramdiskfile;" \
423 "tftp $loadaddr $bootfile;" \
424 "bootm $loadaddr $ramdiskaddr"
425
426#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
427
428#endif
429