LXR uboot/include/fsl

   1/*
   2 * Common internal memory map for some Freescale SoCs
   3 *
   4 * Copyright 2014 Freescale Semiconductor, Inc.
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#ifndef __FSL_SEC_H
  10#define __FSL_SEC_H
  11
  12#include <common.h>
  13#include <asm/io.h>
  14
  15#ifdef CONFIG_SYS_FSL_SEC_LE
  16#define sec_in32(a)       in_le32(a)
  17#define sec_out32(a, v)   out_le32(a, v)
  18#define sec_in16(a)       in_le16(a)
  19#define sec_clrbits32     clrbits_le32
  20#define sec_setbits32     setbits_le32
  21#elif defined(CONFIG_SYS_FSL_SEC_BE)
  22#define sec_in32(a)       in_be32(a)
  23#define sec_out32(a, v)   out_be32(a, v)
  24#define sec_in16(a)       in_be16(a)
  25#define sec_clrbits32     clrbits_be32
  26#define sec_setbits32     setbits_be32
  27#elif defined(CONFIG_SYS_FSL_HAS_SEC)
  28#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  29#endif
  30
  31/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  32#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  33/* RNG4 TRNG test registers */
  34struct rng4tst {
  35#define RTMCTL_PRGM 0x00010000  /* 1 -> program mode, 0 -> run mode */
  36#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
  37                                                    both entropy shifter and
  38                                                    statistical checker */
  39#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
  40                                                    entropy shifter and
  41                                                    statistical checker */
  42#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  43                                                    entropy shifter, raw data
  44                                                    in statistical checker */
  45#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
  46        u32 rtmctl;             /* misc. control register */
  47        u32 rtscmisc;           /* statistical check misc. register */
  48        u32 rtpkrrng;           /* poker range register */
  49#define RTSDCTL_ENT_DLY_MIN     3200
  50#define RTSDCTL_ENT_DLY_MAX     12800
  51        union {
  52                u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
  53                u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
  54        };
  55#define RTSDCTL_ENT_DLY_SHIFT 16
  56#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  57        u32 rtsdctl;            /* seed control register */
  58        union {
  59                u32 rtsblim;    /* PRGM=1: sparse bit limit register */
  60                u32 rttotsam;   /* PRGM=0: total samples register */
  61        };
  62        u32 rtfreqmin;          /* frequency count min. limit register */
  63#define RTFRQMAX_DISABLE       (1 << 20)
  64        union {
  65                u32 rtfreqmax;  /* PRGM=1: freq. count max. limit register */
  66                u32 rtfreqcnt;  /* PRGM=0: freq. count register */
  67        };
  68        u32 rsvd1[40];
  69#define RNG_STATE0_HANDLE_INSTANTIATED  0x00000001
  70        u32 rdsta;              /*RNG DRNG Status Register*/
  71        u32 rsvd2[15];
  72};
  73
  74typedef struct ccsr_sec {
  75        u32     res0;
  76        u32     mcfgr;          /* Master CFG Register */
  77        u8      res1[0x4];
  78        u32     scfgr;
  79        struct {
  80                u32     ms;     /* Job Ring LIODN Register, MS */
  81                u32     ls;     /* Job Ring LIODN Register, LS */
  82        } jrliodnr[4];
  83        u8      res2[0x2c];
  84        u32     jrstartr;       /* Job Ring Start Register */
  85        struct {
  86                u32     ms;     /* RTIC LIODN Register, MS */
  87                u32     ls;     /* RTIC LIODN Register, LS */
  88        } rticliodnr[4];
  89        u8      res3[0x1c];
  90        u32     decorr;         /* DECO Request Register */
  91        struct {
  92                u32     ms;     /* DECO LIODN Register, MS */
  93                u32     ls;     /* DECO LIODN Register, LS */
  94        } decoliodnr[8];
  95        u8      res4[0x40];
  96        u32     dar;            /* DECO Avail Register */
  97        u32     drr;            /* DECO Reset Register */
  98        u8      res5[0x4d8];
  99        struct rng4tst rng;     /* RNG Registers */
 100        u8      res6[0x8a0];
 101        u32     crnr_ms;        /* CHA Revision Number Register, MS */
 102        u32     crnr_ls;        /* CHA Revision Number Register, LS */
 103        u32     ctpr_ms;        /* Compile Time Parameters Register, MS */
 104        u32     ctpr_ls;        /* Compile Time Parameters Register, LS */
 105        u8      res7[0x10];
 106        u32     far_ms;         /* Fault Address Register, MS */
 107        u32     far_ls;         /* Fault Address Register, LS */
 108        u32     falr;           /* Fault Address LIODN Register */
 109        u32     fadr;           /* Fault Address Detail Register */
 110        u8      res8[0x4];
 111        u32     csta;           /* CAAM Status Register */
 112        u32     smpart;         /* Secure Memory Partition Parameters */
 113        u32     smvid;          /* Secure Memory Version ID */
 114        u32     rvid;           /* Run Time Integrity Checking Version ID Reg.*/
 115        u32     ccbvid;         /* CHA Cluster Block Version ID Register */
 116        u32     chavid_ms;      /* CHA Version ID Register, MS */
 117        u32     chavid_ls;      /* CHA Version ID Register, LS */
 118        u32     chanum_ms;      /* CHA Number Register, MS */
 119        u32     chanum_ls;      /* CHA Number Register, LS */
 120        u32     secvid_ms;      /* SEC Version ID Register, MS */
 121        u32     secvid_ls;      /* SEC Version ID Register, LS */
 122        u8      res9[0x6020];
 123        u32     qilcr_ms;       /* Queue Interface LIODN CFG Register, MS */
 124        u32     qilcr_ls;       /* Queue Interface LIODN CFG Register, LS */
 125        u8      res10[0x8fd8];
 126} ccsr_sec_t;
 127
 128#define SEC_CTPR_MS_AXI_LIODN           0x08000000
 129#define SEC_CTPR_MS_QI                  0x02000000
 130#define SEC_CTPR_MS_VIRT_EN_INCL        0x00000001
 131#define SEC_CTPR_MS_VIRT_EN_POR         0x00000002
 132#define SEC_RVID_MA                     0x0f000000
 133#define SEC_CHANUM_MS_JRNUM_MASK        0xf0000000
 134#define SEC_CHANUM_MS_JRNUM_SHIFT       28
 135#define SEC_CHANUM_MS_DECONUM_MASK      0x0f000000
 136#define SEC_CHANUM_MS_DECONUM_SHIFT     24
 137#define SEC_SECVID_MS_IPID_MASK 0xffff0000
 138#define SEC_SECVID_MS_IPID_SHIFT        16
 139#define SEC_SECVID_MS_MAJ_REV_MASK      0x0000ff00
 140#define SEC_SECVID_MS_MAJ_REV_SHIFT     8
 141#define SEC_CCBVID_ERA_MASK             0xff000000
 142#define SEC_CCBVID_ERA_SHIFT            24
 143#define SEC_SCFGR_RDBENABLE             0x00000400
 144#define SEC_SCFGR_VIRT_EN               0x00008000
 145#define SEC_CHAVID_LS_RNG_SHIFT         16
 146#define SEC_CHAVID_RNG_LS_MASK          0x000f0000
 147
 148#define CONFIG_JRSTARTR_JR0             0x00000001
 149
 150struct jr_regs {
 151#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 152        !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 153        u32 irba_l;
 154        u32 irba_h;
 155#else
 156        u32 irba_h;
 157        u32 irba_l;
 158#endif
 159        u32 rsvd1;
 160        u32 irs;
 161        u32 rsvd2;
 162        u32 irsa;
 163        u32 rsvd3;
 164        u32 irja;
 165#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 166        !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 167        u32 orba_l;
 168        u32 orba_h;
 169#else
 170        u32 orba_h;
 171        u32 orba_l;
 172#endif
 173        u32 rsvd4;
 174        u32 ors;
 175        u32 rsvd5;
 176        u32 orjr;
 177        u32 rsvd6;
 178        u32 orsf;
 179        u32 rsvd7;
 180        u32 jrsta;
 181        u32 rsvd8;
 182        u32 jrint;
 183        u32 jrcfg0;
 184        u32 jrcfg1;
 185        u32 rsvd9;
 186        u32 irri;
 187        u32 rsvd10;
 188        u32 orwi;
 189        u32 rsvd11;
 190        u32 jrcr;
 191};
 192
 193/*
 194 * Scatter Gather Entry - Specifies the the Scatter Gather Format
 195 * related information
 196 */
 197struct sg_entry {
 198#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 199        !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
 200        uint32_t addr_lo;       /* Memory Address - lo */
 201        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 202#else
 203        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 204        uint32_t addr_lo;       /* Memory Address - lo */
 205#endif
 206
 207        uint32_t len_flag;      /* Length of the data in the frame */
 208#define SG_ENTRY_LENGTH_MASK    0x3FFFFFFF
 209#define SG_ENTRY_EXTENSION_BIT  0x80000000
 210#define SG_ENTRY_FINAL_BIT      0x40000000
 211        uint32_t bpid_offset;
 212#define SG_ENTRY_BPID_MASK      0x00FF0000
 213#define SG_ENTRY_BPID_SHIFT     16
 214#define SG_ENTRY_OFFSET_MASK    0x00001FFF
 215#define SG_ENTRY_OFFSET_SHIFT   0
 216};
 217
 218#define BLOB_SIZE(x)            ((x) + 32 + 16) /* Blob buffer size */
 219
 220#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
 221/* Job Ring Base Address */
 222#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
 223/* Secure Memory Offset varies accross versions */
 224#define SM_V1_OFFSET 0x0f4
 225#define SM_V2_OFFSET 0xa00
 226/*Secure Memory Versioning */
 227#define SMVID_V2 0x20105
 228#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
 229#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
 230/* CAAM Job Ring 0 Registers */
 231/* Secure Memory Partition Owner register */
 232#define SMCSJR_PO               (3 << 6)
 233/* JR Allocation Error */
 234#define SMCSJR_AERR             (3 << 12)
 235/* Secure memory partition 0 page 0 owner register */
 236#define CAAM_SMPO_0         (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
 237/* Secure memory command register */
 238#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
 239/* Secure memory command status register */
 240#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
 241/* Secure memory access permissions register */
 242#define CAAM_SMAPJR(v, jr, y) \
 243        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
 244/* Secure memory access group 2 register */
 245#define CAAM_SMAG2JR(v, jr, y) \
 246        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
 247/* Secure memory access group 1 register */
 248#define CAAM_SMAG1JR(v, jr, y)  \
 249        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
 250
 251/* Commands and macros for secure memory */
 252#define SM_CMD(v)               (v == 1 ? 0x0 : 0x1E4)
 253#define SM_STATUS(v)            (v == 1 ? 0x8 : 0x1EC)
 254#define SM_PERM(v)              (v == 1 ?  0x10 : 0x4)
 255#define SM_GROUP2(v)            (v == 1 ? 0x14 : 0x8)
 256#define SM_GROUP1(v)            (v == 1 ? 0x18 : 0xC)
 257#define CMD_PAGE_ALLOC          0x1
 258#define CMD_PAGE_DEALLOC        0x2
 259#define CMD_PART_DEALLOC        0x3
 260#define CMD_INQUIRY             0x5
 261#define CMD_COMPLETE            (3 << 14)
 262#define PAGE_AVAILABLE          0
 263#define PAGE_OWNED              (3 << 6)
 264#define PAGE(x)                 (x << 16)
 265#define PARTITION(x)            (x << 8)
 266#define PARTITION_OWNER(x)      (0x3 << (x*2))
 267
 268/* Address of secure 4kbyte pages */
 269#define SEC_MEM_PAGE0           CAAM_ARB_BASE_ADDR
 270#define SEC_MEM_PAGE1           (CAAM_ARB_BASE_ADDR + 0x1000)
 271#define SEC_MEM_PAGE2           (CAAM_ARB_BASE_ADDR + 0x2000)
 272#define SEC_MEM_PAGE3           (CAAM_ARB_BASE_ADDR + 0x3000)
 273
 274#define JR_MID                  2               /* Matches ROM configuration */
 275#define KS_G1                   (1 << JR_MID)   /* CAAM only */
 276#define PERM                    0x0000B008      /* Clear on release, lock SMAP
 277                                                 * lock SMAG group 1 Blob */
 278
 279/* HAB WRAPPED KEY header */
 280#define WRP_HDR_SIZE            0x08
 281#define HDR_TAG                 0x81
 282#define HDR_PAR                 0x41
 283/* HAB WRAPPED KEY Data */
 284#define HAB_MOD                 0x66
 285#define HAB_ALG                 0x55
 286#define HAB_FLG                 0x00
 287
 288/* Partition and Page IDs */
 289#define PARTITION_1     1
 290#define PAGE_1                  1
 291
 292#define ERROR_IN_PAGE_ALLOC     1
 293#define ECONSTRJDESC   -1
 294
 295#endif
 296
 297/* blob_dek:
 298 * Encapsulates the src in a secure blob and stores it dst
 299 * @src: reference to the plaintext
 300 * @dst: reference to the output adrress
 301 * @len: size in bytes of src
 302 * @return: 0 on success, error otherwise
 303 */
 304int blob_dek(const u8 *src, u8 *dst, u8 len);
 305
 306#if defined(CONFIG_ARCH_C29X)
 307int sec_init_idx(uint8_t);
 308#endif
 309int sec_init(void);
 310#endif
 311
 312#endif /* __FSL_SEC_H */
 313