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10#include <common.h>
11#include <errno.h>
12#include <dm.h>
13#include <fdtdec.h>
14#include <malloc.h>
15#include <dm/device-internal.h>
16#include <dm/root.h>
17#include <dm/util.h>
18#include <dm/test.h>
19#include <dm/uclass-internal.h>
20#include <power/pmic.h>
21#include <power/regulator.h>
22#include <power/sandbox_pmic.h>
23#include <test/ut.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27enum {
28 BUCK1,
29 BUCK2,
30 BUCK3,
31 LDO1,
32 LDO2,
33 OUTPUT_COUNT,
34};
35
36enum {
37 DEVNAME = 0,
38 PLATNAME,
39 OUTPUT_NAME_COUNT,
40};
41
42static const char *regulator_names[OUTPUT_COUNT][OUTPUT_NAME_COUNT] = {
43
44 { SANDBOX_BUCK1_DEVNAME, SANDBOX_BUCK1_PLATNAME },
45 { SANDBOX_BUCK2_DEVNAME, SANDBOX_BUCK2_PLATNAME },
46 { SANDBOX_BUCK3_DEVNAME, SANDBOX_BUCK3_PLATNAME },
47 { SANDBOX_LDO1_DEVNAME, SANDBOX_LDO1_PLATNAME},
48 { SANDBOX_LDO2_DEVNAME, SANDBOX_LDO2_PLATNAME},
49};
50
51
52static int dm_test_power_regulator_get(struct unit_test_state *uts)
53{
54 struct dm_regulator_uclass_platdata *uc_pdata;
55 struct udevice *dev_by_devname;
56 struct udevice *dev_by_platname;
57 const char *devname;
58 const char *platname;
59 int i;
60
61 for (i = 0; i < OUTPUT_COUNT; i++) {
62
63
64
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66 devname = regulator_names[i][DEVNAME];
67 platname = regulator_names[i][PLATNAME];
68
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73 ut_assertok(regulator_get_by_devname(devname, &dev_by_devname));
74 ut_asserteq_str(devname, dev_by_devname->name);
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80 ut_assertok(regulator_get_by_platname(platname, &dev_by_platname));
81 uc_pdata = dev_get_uclass_platdata(dev_by_platname);
82 ut_assert(uc_pdata);
83 ut_asserteq_str(platname, uc_pdata->name);
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89 ut_asserteq_ptr(dev_by_devname, dev_by_platname);
90 }
91
92 return 0;
93}
94DM_TEST(dm_test_power_regulator_get, DM_TESTF_SCAN_FDT);
95
96
97static int dm_test_power_regulator_set_get_voltage(struct unit_test_state *uts)
98{
99 struct dm_regulator_uclass_platdata *uc_pdata;
100 struct udevice *dev;
101 const char *platname;
102 int val_set, val_get;
103
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105 platname = regulator_names[BUCK1][PLATNAME];
106 ut_assertok(regulator_get_by_platname(platname, &dev));
107
108 uc_pdata = dev_get_uclass_platdata(dev);
109 ut_assert(uc_pdata);
110
111 val_set = uc_pdata->min_uV;
112 ut_assertok(regulator_set_value(dev, val_set));
113
114 val_get = regulator_get_value(dev);
115 ut_assert(val_get >= 0);
116
117 ut_asserteq(val_set, val_get);
118
119 return 0;
120}
121DM_TEST(dm_test_power_regulator_set_get_voltage, DM_TESTF_SCAN_FDT);
122
123
124static int dm_test_power_regulator_set_get_current(struct unit_test_state *uts)
125{
126 struct dm_regulator_uclass_platdata *uc_pdata;
127 struct udevice *dev;
128 const char *platname;
129 int val_set, val_get;
130
131
132 platname = regulator_names[LDO1][PLATNAME];
133 ut_assertok(regulator_get_by_platname(platname, &dev));
134
135 uc_pdata = dev_get_uclass_platdata(dev);
136 ut_assert(uc_pdata);
137
138 val_set = uc_pdata->min_uA;
139 ut_assertok(regulator_set_current(dev, val_set));
140
141 val_get = regulator_get_current(dev);
142 ut_assert(val_get >= 0);
143
144 ut_asserteq(val_set, val_get);
145
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147 platname = regulator_names[LDO2][PLATNAME];
148 ut_assertok(regulator_get_by_platname(platname, &dev));
149
150 uc_pdata = dev_get_uclass_platdata(dev);
151 ut_assert(uc_pdata);
152 ut_asserteq(-ENODATA, uc_pdata->min_uA);
153 ut_asserteq(-ENODATA, uc_pdata->max_uA);
154
155
156 ut_asserteq(-ENOSYS, regulator_set_current(dev, 0));
157
158 return 0;
159}
160DM_TEST(dm_test_power_regulator_set_get_current, DM_TESTF_SCAN_FDT);
161
162
163static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts)
164{
165 const char *platname;
166 struct udevice *dev;
167 bool val_set = true;
168
169
170 platname = regulator_names[LDO1][PLATNAME];
171 ut_assertok(regulator_get_by_platname(platname, &dev));
172 ut_assertok(regulator_set_enable(dev, val_set));
173
174
175 ut_asserteq(regulator_get_enable(dev), val_set);
176
177 return 0;
178}
179DM_TEST(dm_test_power_regulator_set_get_enable, DM_TESTF_SCAN_FDT);
180
181
182static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts)
183{
184 const char *platname;
185 struct udevice *dev;
186 int val_set = LDO_OM_SLEEP;
187
188
189 platname = regulator_names[LDO1][PLATNAME];
190 ut_assertok(regulator_get_by_platname(platname, &dev));
191 ut_assertok(regulator_set_mode(dev, val_set));
192
193
194 ut_asserteq(regulator_get_mode(dev), val_set);
195
196 return 0;
197}
198DM_TEST(dm_test_power_regulator_set_get_mode, DM_TESTF_SCAN_FDT);
199
200
201static int dm_test_power_regulator_autoset(struct unit_test_state *uts)
202{
203 const char *platname;
204 struct udevice *dev, *dev_autoset;
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214 platname = regulator_names[BUCK1][PLATNAME];
215 ut_assertok(regulator_autoset_by_name(platname, &dev_autoset));
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218 ut_assertok(regulator_get_by_platname(platname, &dev));
219 ut_asserteq_ptr(dev, dev_autoset);
220
221
222 ut_asserteq(regulator_get_value(dev),
223 SANDBOX_BUCK1_AUTOSET_EXPECTED_UV);
224 ut_asserteq(regulator_get_current(dev),
225 SANDBOX_BUCK1_AUTOSET_EXPECTED_UA);
226 ut_asserteq(regulator_get_enable(dev),
227 SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE);
228
229 return 0;
230}
231DM_TEST(dm_test_power_regulator_autoset, DM_TESTF_SCAN_FDT);
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239struct setting {
240 int voltage;
241 int current;
242 bool enable;
243};
244
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250
251static const char *platname_list[] = {
252 SANDBOX_LDO1_PLATNAME,
253 SANDBOX_LDO2_PLATNAME,
254 NULL,
255};
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265static const struct setting expected_setting_list[] = {
266 [0] = {
267 .voltage = SANDBOX_LDO1_AUTOSET_EXPECTED_UV,
268 .current = SANDBOX_LDO1_AUTOSET_EXPECTED_UA,
269 .enable = SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE,
270 },
271 [1] = {
272 .voltage = SANDBOX_LDO2_AUTOSET_EXPECTED_UV,
273 .current = SANDBOX_LDO2_AUTOSET_EXPECTED_UA,
274 .enable = SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE,
275 },
276};
277
278static int list_count = ARRAY_SIZE(expected_setting_list);
279
280
281static int dm_test_power_regulator_autoset_list(struct unit_test_state *uts)
282{
283 struct udevice *dev_list[2], *dev;
284 int i;
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302 ut_assertok(regulator_list_autoset(platname_list, dev_list, false));
303
304 for (i = 0; i < list_count; i++) {
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306 ut_assert(dev_list[i]);
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309 ut_assertok(regulator_get_by_platname(platname_list[i], &dev));
310 ut_asserteq_ptr(dev_list[i], dev);
311
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313 ut_asserteq(regulator_get_value(dev_list[i]),
314 expected_setting_list[i].voltage);
315
316
317 ut_asserteq(regulator_get_current(dev_list[i]),
318 expected_setting_list[i].current);
319
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321 ut_asserteq(regulator_get_enable(dev_list[i]),
322 expected_setting_list[i].enable);
323 }
324
325 return 0;
326}
327DM_TEST(dm_test_power_regulator_autoset_list, DM_TESTF_SCAN_FDT);
328