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7#ifndef _ASM_ARCH_CLOCK_H
8#define _ASM_ARCH_CLOCK_H
9
10
11#define RKCLK_PLL_MODE_SLOW 0
12#define RKCLK_PLL_MODE_NORMAL 1
13
14enum {
15 ROCKCHIP_SYSCON_NOC,
16 ROCKCHIP_SYSCON_GRF,
17 ROCKCHIP_SYSCON_SGRF,
18 ROCKCHIP_SYSCON_PMU,
19 ROCKCHIP_SYSCON_PMUGRF,
20 ROCKCHIP_SYSCON_PMUSGRF,
21 ROCKCHIP_SYSCON_CIC,
22 ROCKCHIP_SYSCON_MSCH,
23};
24
25
26enum rk_clk_id {
27 CLK_OSC,
28 CLK_ARM,
29 CLK_DDR,
30 CLK_CODEC,
31 CLK_GENERAL,
32 CLK_NEW,
33
34 CLK_COUNT,
35};
36
37static inline int rk_pll_id(enum rk_clk_id clk_id)
38{
39 return clk_id - 1;
40}
41
42struct sysreset_reg {
43 unsigned int glb_srst_fst_value;
44 unsigned int glb_srst_snd_value;
45};
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57static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
58{
59 uint clk_div;
60
61 clk_div = input_rate / output_rate;
62 clk_div = (clk_div + 1) & 0xfffe;
63
64 return clk_div;
65}
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71
72void *rockchip_get_cru(void);
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79void *rockchip_get_pmucru(void);
80
81struct rk3288_cru;
82struct rk3288_grf;
83
84void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
85
86int rockchip_get_clk(struct udevice **devp);
87
88#endif
89