LXR uboot/arch/arm/mach-mvebu/armada8k/cpu.c

   1/*
   2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <dm.h>
   9#include <fdtdec.h>
  10#include <libfdt.h>
  11#include <asm/io.h>
  12#include <asm/system.h>
  13#include <asm/arch/cpu.h>
  14#include <asm/arch/soc.h>
  15#include <asm/armv8/mmu.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19/* Armada 7k/8k */
  20#define MVEBU_RFU_BASE                  (MVEBU_REGISTER(0x6f0000))
  21#define RFU_GLOBAL_SW_RST               (MVEBU_RFU_BASE + 0x84)
  22#define RFU_SW_RESET_OFFSET             0
  23
  24/*
  25 * The following table includes all memory regions for Armada 7k and
  26 * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
  27 * define these regions at the beginning of the struct so that they
  28 * can be easier removed later dynamically if an Armada 7k device is detected.
  29 * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
  30 */
  31#define ARMADA_7K8K_COMMON_REGIONS_START        2
  32static struct mm_region mvebu_mem_map[] = {
  33        /* Armada 80x0 memory regions include the CP1 (slave) units */
  34        {
  35                /* SRAM, MMIO regions - CP110 slave region */
  36                .phys = 0xf4000000UL,
  37                .virt = 0xf4000000UL,
  38                .size = 0x02000000UL,   /* 32MiB internal registers */
  39                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  40                         PTE_BLOCK_NON_SHARE
  41        },
  42        {
  43                /* PCI CP1 regions */
  44                .phys = 0xfa000000UL,
  45                .virt = 0xfa000000UL,
  46                .size = 0x04000000UL,   /* 64MiB CP110 slave PCI space */
  47                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48                         PTE_BLOCK_NON_SHARE
  49        },
  50        /* Armada 80x0 and 70x0 common memory regions start here */
  51        {
  52                /* RAM */
  53                .phys = 0x0UL,
  54                .virt = 0x0UL,
  55                .size = 0x80000000UL,
  56                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  57                         PTE_BLOCK_INNER_SHARE
  58        },
  59        {
  60                /* SRAM, MMIO regions - AP806 region */
  61                .phys = 0xf0000000UL,
  62                .virt = 0xf0000000UL,
  63                .size = 0x01000000UL,   /* 16MiB internal registers */
  64                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  65                         PTE_BLOCK_NON_SHARE
  66        },
  67        {
  68                /* SRAM, MMIO regions - CP110 master region */
  69                .phys = 0xf2000000UL,
  70                .virt = 0xf2000000UL,
  71                .size = 0x02000000UL,   /* 32MiB internal registers */
  72                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  73                         PTE_BLOCK_NON_SHARE
  74        },
  75        {
  76                /* PCI CP0 regions */
  77                .phys = 0xf6000000UL,
  78                .virt = 0xf6000000UL,
  79                .size = 0x04000000UL,   /* 64MiB CP110 master PCI space */
  80                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  81                         PTE_BLOCK_NON_SHARE
  82        },
  83        {
  84                0,
  85        }
  86};
  87
  88struct mm_region *mem_map = mvebu_mem_map;
  89
  90void enable_caches(void)
  91{
  92        /*
  93         * Armada 7k is not equipped with the CP110 slave CP. In case this
  94         * code runs on an Armada 7k device, lets remove the CP110 slave
  95         * entries from the memory mapping by moving the start to the
  96         * common regions.
  97         */
  98        if (of_machine_is_compatible("marvell,armada7040"))
  99                mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
 100
 101        icache_enable();
 102        dcache_enable();
 103}
 104
 105void reset_cpu(ulong ignored)
 106{
 107        u32 reg;
 108
 109        reg = readl(RFU_GLOBAL_SW_RST);
 110        reg &= ~(1 << RFU_SW_RESET_OFFSET);
 111        writel(reg, RFU_GLOBAL_SW_RST);
 112}
 113
 114/*
 115 * TODO - implement this functionality using platform
 116 *        clock driver once it gets available
 117 * Return NAND clock in Hz
 118 */
 119u32 mvebu_get_nand_clock(void)
 120{
 121        unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
 122        unsigned long NF_CLOCK_SEL_MASK = 0x1;
 123        u32 reg;
 124
 125        reg = readl(NAND_FLASH_CLK_CTRL);
 126        if (reg & NF_CLOCK_SEL_MASK)
 127                return 400 * 1000000;
 128        else
 129                return 250 * 1000000;
 130}
 131